參數(shù)資料
型號(hào)： XR17C152CM-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 20/62頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17C152 100TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
á
XR17C152
REV. 1.2.0
5V PCI BUS DUAL UART
27
4.3
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR bits 1-4 and an LSR interrupt is generated immediately if IER bit-2 is enabled. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the LSR bits are
immediately updated to reflect the status of the data byte in the RHR. The RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach
the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time.
The RHR interrupt is enabled by IER bit-0.
4.3.1
Receive Holding Register (RHR) - Read-Only
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. The RHR is also part of the receive FIFO of 64
bytes by 11-bit wide, 3 extra bits are for the error tags in LSR. When the FIFO is enabled by FCR bit-0, the
RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is
loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR
bits 1-4.
4.3.2
Receiver Operation in non-FIFO Mode
FIGURE 12. RECEIVER OPERATION IN NON-FIFO MODE
Re c e iv e Da ta Sh ift
R egister (R S R )
Re c e iv e
D a ta B y te
and E rr o rs
RHR I n te r ru p t (IS R b it -2 )
Re c e iv e Da ta
H o ld ing R egist e r
(RHR)
16X or 8X C lo c k
(8 XM O D E Re g is t e r )
Re c e iv e Da t a Ch a r a c te r s
Da ta Bit
Va lid a t io n
Er ro r
Ta g s in
LS R bits
3:1
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XR17C152IM 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS DUAL UART
XR17C152IM-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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XR17C154_05 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS QUAD UART
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