NAME P
參數(shù)資料
型號(hào): XR17C152CM-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 23/62頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17C152 100TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
á
XR17C152
REV. 1.2.0
5V PCI BUS DUAL UART
3
PIN DESCRIPTIONS
Pin Description
NAME
PIN #TYPE
DESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
86
I
Bus reset input (active low). It resets the PCI local bus configuration space
registers, device configuration registers and UART channel registers to the
default condition, see Table 19 on page 48.
CLK
87
I
Bus clock input of up to 33MHz at 5V.
AD31-AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
90-97,
2-9,
24-31,
35-42
I/O
Address data lines [31:0] (bidirectional).
FRAME#
13
I
Bus transaction cycle frame (active low). It indicates the beginning and dura-
tion of an access.
C/BE3#-C/BE0#
98, 12,
21, 34
I
Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enables during the data
phase.
IRDY#
14
I
Initiator Ready (active low). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
TRDY#
15
O
Target Ready (active low).
STOP#
17
O
Target request to stop current transaction (active low).
IDSEL
99
I
Initialization device select (active high).
DEVSEL#
16
O
Device select to the XR17C152 (active low).
INTA#
85
OD
Device interrupt from XR17C152 (open drain, active low).
PAR
20
I/O
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high).
PERR#
18
O
Data Parity error indicator, except for Special Cycle transactions (active low).
Optional in bus target application.
SERR#
19
OD
System error indicator, Address parity or Data parity during Special Cycle
transactions (open drain, active low). Optional in bus target application.
MODEM OR SERIAL I/O INTERFACE
TX0
73
O
UART channel 0 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
RX0
66
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles HIGH while infrared RXD input idles LOW. In the infrared mode, the
polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit
is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a
logic 1, a HIGH on the RXD input is considered a space.
RTS0#
71
O
UART channel 0 Request to Send or general purpose output (active low). If
this output is not used, leave it unconnected.
CTS0#
67
I
UART channel 0 Clear to Send or general purpose input (active low). This
input should be connected to VCC when not used.
DTR0#
72
O
UART channel 0 Data Terminal Ready or general purpose output (active low).
If this output is not used, leave it unconnected.
DSR0#
68
I
UART channel 0 Data Set Ready or general purpose input (active low). This
input should be connected to VCC when not used.
CD0#
69
I
UART channel 0 Carrier Detect or general purpose input (active low). This
input should be connected to VCC when not used.
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