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參數(shù)資料
| 型號： | XR17C152CM-0A-EVB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17C152 100TQFP |
| 標準包裝： | 1 |
| 系列： | * |
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XR17C152
á
5V PCI BUS DUAL UART
REV. 1.2.0
28
4.3.3
Receiver Operation with FIFO
4.4
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver
FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request the remote unit to suspend/
restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart the local transmitter.
The auto RTS/CTS or DTR/DSR flow control features are individually selected to fit specific application
requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control
signals.
Auto RTS flow control must be started by asserting the RTS# output pin LOW (MCR bit-1 = 1). Similarly, Auto
DTR flow control must be started by asserting the DTR# output pin LOW (MCR bit-0 = 1). Figure 14 shows in
detail how automatic hardware flow control works.
FIGURE 13. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
TABLE 10: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION
MCR BIT-2
EFR BIT-7
EFR BIT-6
HARDWARE FLOW CONTROL SELECTION
0
1
X
Auto CTS Flow Control Enabled
0
X
1
Auto RTS Flow Control Enabled
1
X
Auto DSR Flow Control Enabled
1
X
1
Auto DTR Flow Control Enabled
X
0
No Hardware Flow Control
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Sampling
Clock (8XMODE Reg.)
E
rror
Tags
(64-sets)
E
rror
Tags
i
n
LS
R
bits
3:1
64 bytes by 11-
bit wide FIFO
Receive Data Characters
FIFO Trigger=48
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data fills to 56
Data falls to 40
Data Bit
Validation
Receive Data
FIFO
(64-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17C152CM-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17C152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS DUAL UART |
| XR17C152IM-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17C154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS QUAD UART |
| XR17C154_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS QUAD UART |
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