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| 型號： | XC56L307VF160 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 86/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT FIXED POINT 196-BGA |
| 標準包裝： | 126 |
| 系列： | DSP563xx |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 160MHz |
| 非易失內存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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DSP56L307 Technical Data, Rev. 6
4-4
Freescale Semiconductor
Design Considerations
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-
case operation conditions—not necessarily a real application case. The typical internal current (ICCItyp) value
reflects the average switching of the internal buses on typical operating conditions.
Perform the following steps for applications that require very low current consumption:
1.
Set the EBD bit when you are not accessing external memory.
2.
Minimize external memory accesses, and use internal memory accesses.
3.
Minimize the number of pins that are switching.
4.
Minimize the capacitive load on the pins.
5.
Connect the unused inputs to pull-up or pull-down resistors.
6.
Disable unused peripherals.
7.
Disable unused pin activity (for example, CLKOUT, XTAL).
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize
specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark
power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current
measurements, and the following equation to derive the current-per-MIPS value.
Equation 5:
Where:
ItypF2
=
current at F2
ItypF1
=
current at F1
F2
=
high frequency (any specified operating frequency)
F1
=
low frequency (any specified operating frequency lower than F2)
Note:
F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The
degree of difference between F1 and F2 determines the amount of precision with which the current rating
can be determined for an application.
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no
test that replicates these exact numbers. These observations were measured on a limited number of parts and were
not verified over the entire temperature and voltage ranges.
4.4.1
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a
given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 2-
2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF
≤4, this skew is
greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10
and input frequencies greater than 10 MHz, this skew is between
1.4 ns and +3.2 ns.
MIPS
I
MHz
I
typF2
I
typF1
–
()
F2
F1
–
(
==
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| XC56L307VL150 | 功能描述:IC DSP 24BIT 150MHZ 196-MABGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:DSP563xx 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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| XC5A0122 | 制造商:Omron Electronic Components LLC 功能描述:CONN DIN 41612 PL 100 POS 2.54MM SLDR RA TH - Bulk 制造商:Omron Electronic Components LLC 功能描述:CONNECTR 100POS RT-ANGL TERM DIN 制造商:Omron Electronic Components LLC 功能描述:Conn DIN 41612 PL 100 POS 2.54mm Solder RA Thru-Hole |
| XC5A-0122 | 功能描述:DIN 41612 連接器 CONNECTOR RoHS:否 制造商:HARTING 系列:har-bus 64 產品類型:Plugs 排數:5 位置/觸點數量:160 安裝角:Right 類型:Shrouded Header 端接類型:Solder 外殼材料: 觸點材料: 觸點電鍍: |
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