參數(shù)資料
型號(hào): XC56L307VF160
廠商: Freescale Semiconductor
文件頁數(shù): 63/104頁
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED POINT 196-BGA
標(biāo)準(zhǔn)包裝: 126
系列: DSP563xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 160MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤
ESSI0/ESSI1 Timing
DSP56L307 Technical Data, Rev. 6
Freescale Semiconductor
2-41
452
TXC rising edge to data out enable from high impedance
31.0
17.0
x ck
i ck
ns
453
TXC rising edge to transmitter 0 drive enable assertion
34.0
20.0
x ck
i ck
ns
454
TXC rising edge to data out valid
35 + 0.5
× TC
38.1
21.0
x ck
i ck
ns
455
TXC rising edge to data out high impedance7
31.0
16.0
x ck
i ck
ns
456
TXC rising edge to transmitter 0 drive enable deassertion
7
34.0
20.0
x ck
i ck
ns
457
FST input (bl, wr) set-up time before TXC falling edge6
2.0
21.0
x ck
i ck
ns
458
FST input (wl) to data out enable from high impedance
27.0
ns
459
FST input (wl) to transmitter 0 drive enable assertion
31.0
ns
460
FST input (wl) set-up time before TXC falling edge
2.0
21.0
x ck
i ck
ns
461
FST input hold time after TXC falling edge
4.0
0.0
x ck
i ck
ns
462
Flag output valid after TXC rising edge
32.0
18.0
x ck
i ck
ns
Notes:
1.
VCCQL = 2.5 V ± 0.25 V; TJ = 40°C to +100 °C, CL = 50 pF.
2.
i ck = internal clock
x ck = external clock
i ck a = internal clock, Asynchronous mode
(asynchronous implies that TXC and RXC are two different clocks)
i ck s = internal clock, Synchronous mode
(synchronous implies that TXC and RXC are the same clock)
3.
bl = bit length
wl = word length
wr = word length relative
4.
TXC (SCK pin) = transmit clock
RXC (SC0 or SCK pin) = receive clock
FST (SC2 pin) = transmit frame sync
FSR (SC1 or SC2 pin) receive frame sync
5.
For the internal clock, the external clock cycle is defined by ICYC and the ESSI Control Register (SSICR).
6.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before first bit clock (same as Bit Length Frame Sync signal), until the one
before last bit clock of the first word in frame.
7.
Periodically sampled and not 100 per cent tested
Table 2-20.
ESSI Timings at 160 MHz (Continued)
No.
Characteristics1,2,3
Symbol
Expression
Min
Max
Condi-
tion4
Unit
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