參數(shù)資料
型號： XC56L307VF160
廠商： Freescale Semiconductor
文件頁數(shù)： 25/104頁
文件大?。?/td> 0K
描述： IC DSP 24BIT FIXED POINT 196-BGA
標準包裝： 126
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 160MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
AC Electrical Characteristics
DSP56L307 Technical Data, Rev. 6
Freescale Semiconductor
2-7
2.4.4
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing6
No.
Characteristics
Expression
100 MHz
160 MHz
Unit
Min
Max
Min
Max
8
Delay from RESET assertion to all pins at reset value3
—
26.0
—
26.0
ns
9
Required RESET duration
4
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During STOP, XTAL disabled (PCTL Bit 16 = 0)
During STOP, XTAL enabled (PCTL Bit 16 = 1)
During normal operation
Minimum:
50
× ET
C
1000
× ETC
75000
× ETC
75000
× ET
C
2.5
× TC
2.5
× TC
500.0
10.0
0.75
25.0
—
313.06
6.25
0.47
15.6
—
ns
s
ms
ns
10
Delay from asynchronous RESET deassertion to first external
address output (internal reset deassertion)
5
Minimum
Maximum
3.25
× T
C + 2.0
20.25
× TC + 10
34.5
—
211.5
22.3
—
134.0
ns
13
Mode select set-up time
30.0
—
30.0
—
ns
14
Mode select hold time
0.0
—
0.0
—
ns
15
Minimum edge-triggered interrupt request assertion width
6.6
—
6.6
—
ns
16
Minimum edge-triggered interrupt request deassertion width
6.6
—
6.6
—
ns
17
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
Minimum:
4.25
× TC + 2.0
7.25
× TC + 2.0
44.5
74.5
—
28.6
47.3
—
ns
18
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
Minimum:
10
× TC + 5.0
105.0
—
67.5
—
ns
19
Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
Maximum:
(WS + 3.75)
× T
C – 10.94
—
Note 8
—
Note 8
ns
20
Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
Maximum:
(WS + 3.25)
× TC – 10.94
—
Note 8
—
Note 8
ns
21
Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS
≥ 4
Maximum:
(WS + 3.5)
× TC – 10.94
(WS + 3.5)
× T
C – 10.94
(WS + 3)
× TC – 10.94
(WS + 2.5)
× TC – 10.94
—
Note 8
—
Note 8
ns
24
Duration for IRQA assertion to recover from Stop state
5.9
—
5.9
—
ns
25
Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)2, 3
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
Delay)
PLC
× ETC × PDF + (128 K
PLC/2) × T
C
PLC
× ETC × PDF + (23.75
± 0.5) × TC
(8.25
± 0.5) × T
C
1.3
232.5
ns
77.5
13.6
12.3
ms
87.5
1.3
232.5
ns
48.4
13.6
12.3
ms
54.7
ms
ns
26
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)2, 3
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop
delay)
Minimum:
PLC
× ETC × PDF + (128K
PLC/2)
× T
C
PLC
× ETC × PDF +
(20.5
± 0.5) × TC
5.5
× T
C
13.6
12.3
55.0
—
13.6
12.3
34.4
—
ms
ns
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