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參數(shù)資料
| 型號(hào)： | XC3S1200E-5FGG400C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 218/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 1200K 400FBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 2168 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 304 |
| 門數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 400-BGA |
| 供應(yīng)商設(shè)備封裝： | 400-FBGA（21x21） |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
90
support byte-wide data. However, after configuration, the
FPGA supports either x8 or x16 modes. In x16 mode, up to
eight additional user I/O pins are required for the upper data
bits, D[15:8].
Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is
simple, but does require a precaution. Various Flash PROM
vendors use slightly different interfaces to support both x8
and x16 modes. Some vendors (Intel, Micron, some
STMicroelectronics devices) use a straightforward interface
with pin naming that matches the FPGA connections.
However, the PROM’s A0 pin is wasted in x16 applications
and a separate FPGA user-I/O pin is required for the D15
data line. Fortunately, the FPGA A0 pin is still available as a
user I/O after configuration, even though it connects to the
Flash PROM.
Other vendors (AMD, Atmel, Silicon Storage Technology,
some STMicroelectronics devices) use a pin-efficient
interface but change the function of one pin, called
IO15/A-1, depending if the PROM is in x8 or x16 mode. In
x8 mode, BYTE# = 0, this pin is the least-significant
address line. The A0 address line selects the halfword
location. The A-1 address line selects the byte location.
When in x16 mode, BYTE# = 1, the IO15/A-1 pin becomes
the most-significant data bit, D15 because byte addressing
is not required in this mode. Check to see if the Flash
PROM has a pin named “IO15/A-1” or “DQ15/A-1”. If so, be
careful to connect x8/x16 Flash PROMs correctly, as shown
in Table 63. Also, remember that the D[14:8] data
connections require FPGA user I/O pins but that the D15
data is already connected for the FPGA’s A0 pin.
Some x8/x16 Flash PROMs have a long setup time
requirement on the BYTE# signal. For the FPGA to
configure correctly, the PROM must be in x8 mode with
BYTE# = 0 at power-on or when the FPGA’s PROG_B pin is
pulsed Low. If required, extend the BYTE# setup time for a
3.3V PROM using an external 680
Ω pull-down resistor on
the FPGA’s LDC2 pin or by delaying assertion of the CSI_B
select input to the FPGA.
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in Figure 59. Use BPI mode
(M[2:0] = <0:1:0> or <0:1:1>) for the FPGA connected to
the parallel NOR Flash PROM and Slave Parallel mode
(M[2:0] = <1:1:0>) for all downstream FPGAs in the
daisy-chain. If there are more than two FPGAs in the chain,
then last FPGA in the chain can be from any Xilinx FPGA
family. However, all intermediate FPGAs located in the
chain between the first and last FPGAs must from either the
Spartan-3E or Virtex-5 FPGA families.
After the master FPGA—the FPGA on the left in the
diagram—finishes loading its configuration data from the
parallel Flash PROM, the master device continues
generating addresses to the Flash PROM and asserts its
CSO_B output Low, enabling the next FPGA in the
daisy-chain. The next FPGA then receives parallel
configuration data from the Flash PROM. The master
FPGA’s CCLK output synchronizes data capture.
If HSWAP = 1, an external 4.7k
Ω pull-up resistor must be
added on the CSO_B pin. If HSWAP = 0, no external pull-up
is necessary.
Design Note
BPI mode daisy chain software support is available starting
in ISE 8.2i.
Table 63: FPGA Connections to Flash PROM with IO15/A-1 Pin
FPGA Pin
Connection to Flash PROM with
IO15/A-1 Pin
x8 Flash PROM Interface After
FPGA Configuration
x16 Flash PROM Interface After
FPGA Configuration
LDC2
BYTE#
Drive LDC2 Low or leave
unconnected and tie PROM BYTE#
input to GND
Drive LCD2 High
LDC1
OE#
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
output-enable control
LDC0
CS#
Active-Low Flash PROM chip-select
control
Active-Low Flash PROM chip-select
control
HDC
WE#
Flash PROM write-enable control
A[23:1]
A[n:0]
A0
IO15/A-1
IO15/A-1 is the least-significant
address input
IO15/A-1 is the most-significant data
line, IO15
D[7:0]
IO[7:0]
User I/O
Upper data lines IO[14:8] not required
unless used as x16 Flash interface after
configuration
Upper data lines IO[14:8] not
required
IO[14:8]
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| XC3S1200E-5FGG400I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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