參數(shù)資料
型號(hào): XC3S1200E-5FGG400C
廠商: Xilinx Inc
文件頁數(shù): 207/227頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3E 1200K 400FBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-3E
LAB/CLB數(shù): 2168
邏輯元件/單元數(shù): 19512
RAM 位總計(jì): 516096
輸入/輸出數(shù): 304
門數(shù): 1200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 400-BGA
供應(yīng)商設(shè)備封裝: 400-FBGA(21x21)
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁當(dāng)前第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁
Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
80
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply
voltage. All of the FPGA’s SPI Flash interface signals are
within I/O Bank 2. Consequently, the FPGA’s VCCO_2
supply voltage must also be 3.3V to match the SPI Flash
PROM.
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 66, page 103. The FPGA waits
for its three power supplies
VCCINT, VCCAUX, and VCCO
to I/O Bank 2 (VCCO_2)
to reach their respective
power-on thresholds before beginning the configuration
process.
The SPI Flash PROM is powered by the same voltage
supply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their VCC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 s as shown in
Table 56. For other vendors, this delay is as much as 20 ms.
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other VCCINT and
VCCAUX supplies, and consequently, there is no issue.
However, if the 3.3V supply feeding the FPGA's VCCO_2
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
If the FPGA's VCCINT and VCCAUX supplies are already
valid, then the FPGA waits for VCCO_2 to reach its
minimum threshold voltage before starting configuration.
This threshold voltage is labeled as VCCO2T in Table 74 of
Module 3 and ranges from approximately 0.4V to 1.0V,
substantially lower than the SPI Flash PROM's minimum
voltage. Once all three FPGA supplies reach their
respective Power On Reset (POR) thresholds, the FPGA
starts the configuration process and begins initializing its
internal configuration memory. Initialization requires
approximately 1 ms (TPOR, minimum in Table 111 of
Module 3, after which the FPGA de-asserts INIT_B, selects
the SPI Flash PROM, and starts sending the appropriate
read command. The SPI Flash PROM must be ready for
Table 56: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Vendor
SPI Flash PROM
Part Number
Data Sheet Minimum Time from VCC min to Select = Low
Symbol
Value
Units
STMicroelectronics
M25Pxx
TVSL
10
μs
Spansion
S25FLxxxA
tPU
10
ms
NexFlash
NX25xx
TVSL
10
μs
Macronix
MX25Lxxxx
tVSL
10
μs
Silicon Storage Technology
SST25LFxx
TPU-READ
10
μs
Programmable Microelectronics
Corporation
Pm25LVxxx
TVCS
50
μs
Atmel Corporation
AT45DBxxxD
tVCSL
30
μs
AT45DBxxxB
20
ms
X-Ref Target - Figure 55
Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
FPGA VCCO_2 minimum
Power On Reset Voltage
(V
CCO2T)
SPI Flash PROM
minimum voltage
SPI Flash available for
read operations
SPI Flash
(t
VSL)
SPI Flash cannot be selected
FPGA initializes configuration
memory
3.3V Supply
FPGA accesses
SPI Flash PROM
Time
SPI Flash PROM must
be ready for FPGA
access, otherwise delay
FPGA configuration
DS312-2_50b_110206
(T
POR)
(VCCINT, VCCAUX
already valid)
PROM CS
delay
相關(guān)PDF資料
PDF描述
0511171605 CONN RETAINER FOR 16POS HOUSING
XC3S1200E-4FGG400I IC FPGA SPARTAN-3E 1200K 400FBGA
GSC43DTEI CONN EDGECARD 86POS .100 EYELET
XC6SLX25T-N3FGG484I IC FPGA SPARTAN-6 484FBGA
XC3S1000-4FGG456I SPARTAN-3A FPGA 1M STD 456-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3S1200E-5FGG400I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family
XC3S1200E-5FGG484C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family
XC3S1200E-5FGG484I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family
XC3S1200E-5FT256C 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 1.2M GATES 19512 CELLS 657MHZ 90NM 1.2V 256F - Trays
XC3S1200E-5FT256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family