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參數(shù)資料
| 型號： | XC3S1200E-5FGG400C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 216/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 1200K 400FBGA |
| 標準包裝： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 2168 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計： | 516096 |
| 輸入/輸出數(shù)： | 304 |
| 門數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 400-BGA |
| 供應商設(shè)備封裝： | 400-FBGA（21x21） |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
89
Compatible Flash Families
The Spartan-3E BPI configuration interface operates with a
wide variety of x8 or x8/x16 parallel NOR Flash devices.
Table 61 provides a few Flash memory families that operate
with the Spartan-3E BPI interface. Consult the data sheet
for the desired parallel NOR Flash to determine its suitability
The basic timing requirements and waveforms are provided
(Module 3).
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest
frequency and increases its frequency for the remainder of
the configuration process if so specified in the configuration
bitstream. The maximum frequency is specified using the
ConfigRate bitstream generator option.
Table 62 shows the maximum ConfigRate settings for
various typical PROM read access times over the
Commercial temperature operating range. See Byte
and UG332 for more detailed information. Despite using
slower ConfigRate settings, BPI mode is equally fast as the
other configuration modes. In BPI mode, data is accessed
at the ConfigRate frequency and internally serialized with
an 8X clock frequency.
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all
pins connected to the parallel Flash PROM are available as
user I/Os.
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
Because all the interface pins are user I/Os after
configuration, the FPGA application can continue to use the
interface pins to communicate with the parallel Flash
PROM. Parallel Flash PROMs are available in densities
ranging from 1 Mbit up to 128 Mbits and beyond. However,
a single Spartan-3E FPGA requires less than 6 Mbits for
configuration. If desired, use a larger parallel Flash PROM
to contain additional non-volatile application data, such as
MicroBlaze processor code, or other user data, such as
serial numbers and Ethernet MAC IDs. In such an example,
the FPGA configures from parallel Flash PROM. Then using
FPGA logic after configuration, a MicroBlaze processor
embedded within the FPGA can either execute code directly
from parallel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
The address, data, and LDC1 (OE#) and HDC (WE#)
control signals are common to all parallel peripherals.
Connect the chip-select input on each additional peripheral
to one of the FPGA user I/O pins. If HSWAP = 0 during
configuration, the FPGA holds the chip-select line High via
an internal pull-up resistor. If HSWAP = 1, connect the
select line to +3.3V via an external 4.7 k
Ω pull-up resistor to
avoid spurious read or write operations. After configuration,
drive the select line Low to select the desired peripheral.
Refer to the individual peripheral data sheet for specific
interface and communication protocol requirements.
The FPGA optionally supports a 16-bit peripheral interface
by driving the LDC2 (BYTE#) control pin High after
configuration. See Precautions Using x8/x16 Flash PROMs
for additional information.
The FPGA provides up to 24 address lines during
configuration, addressing up to 128 Mbits (16 Mbytes). If
using a larger parallel PROM, connect the upper address
lines to FPGA user I/O. During configuration, the upper
address lines will be pulled High if HSWAP = 0. Otherwise,
use external pull-up or pull-down resistors on these address
lines to define their values during configuration.
Precautions Using x8/x16 Flash PROMs
Most low- to mid-density PROMs are byte-wide (x8)
only. Many higher-density Flash PROMs support both
byte-wide (x8) and halfword-wide (x16) data paths and
include a mode input called BYTE# that switches between
x8 or x16. During configuration, Spartan-3E FPGAs only
Table 61: Compatible Parallel NOR Flash Families
Flash Vendor
Flash Memory Family
M29W, J3D StrataFlash
S29
MX29
Table 62: Maximum ConfigRate Settings for Parallel
Flash PROMs (Commercial Temperature Range)
Flash Read Access Time
Maximum ConfigRate
Setting
250 ns
3
115 ns
6
45 ns
12
D
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| XC3S1200E-5FGG400I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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