
W9968CF
- 58 -
Power-on Default:
XXXXH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAPUSA0[15:0]
Bits 15-0 Capture U Frame Buffer 0 Start Address Low
A 21-bit value specifies the WORD offset from the start of the frame buffer for U
components (planar mode) of the captured video. It is not used if the captured video is in
packed mode. Buffer 0 is always used, no matter double buffering is enabled or disabled.
This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR1B_4-0.
Capture U Frame Buffer 0 Start Address High Register (CR25)
Read/Write
Power-on Default:
Index: 0025H
XXXXH
uC Address: 4AH - 4BH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CAPUSA0[20:16]
Bits 15-5 Reserved
Bits 4-0
CAPUSA0[20:16]
Capture U Frame Buffer 1 Start Address Low Register (CR26)
Read/Write
Power-on Default:
Index: 0026H
XXXXH
uC Address: 4CH - 4DH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAPUSA1[15:0]
Bits 15-0 Capture U Frame Buffer 1 Start Address Low
A 21-bit value specifies the WORD offset from the start of the frame buffer for U
components (planar mode) of the captured video. It is not used if the captured video is in
packed mode. Buffer 1 is not used if double buffering is disabled. This register contains 16
lower-order bits of the value. Bits 20-16 are located at CR1D_4-0.
Capture U Frame Buffer 1 Start Address High Register (CR27)
Read/Write
Index: 0027H
uC Address: 4EH - 4FH