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參數(shù)資料
| 型號： | W9968CF |
| 英文描述： | Digital Camera |
| 中文描述： | 數(shù)碼相機(jī) |
| 文件頁數(shù)： | 23/78頁 |
| 文件大?。?/td> | 814K |
| 代理商： | W9968CF |
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W9968CF
Publication Release Date: May 1999
- 23 - Revision A2
7.2 DRAM Control and Interface
The W9968CF supports 256K
×
16 and 1M
×
16 SDRAM or EDO DRAM in a 0.5 ~ 4 Mbytes configuration
with 16-bit data bus. A single 1M
×
16, -15 or above, SDRAM is recommended for better
cost/performance.
7.2.1 DRAM Access Arbitration
The DRAM arbiter helps to maximize performance by orchestrating memory access requests from
internal engines. Two priority levels are defined for these requests:
First priority: DRAM refresh request and SDRAM mode register write request
Second priority: Capture FIFO write request, DCT read request, VLE read request, VLE FIFO
write request, USB FIFO read request, and USB control read/write request
Programmable FIFO status are provided by the Capture FIFO, VLE FIFO, and USB FIFO such that the
DRAM Controller arbitrates according to these FIFO status to prevent any video data loss and to
achieve the best performance.
7.2.2 DRAM Interface
The DRAM controller provides many programmable controls for the DRAM operations which include:
DRAM Type: supports SDRAM and EDO DRAM
DRAM Address: programmable 9-bit (256K
×
EDO DRAM), 10-bit (1M
×
EDO DRAM or 256K
×
SDRAM), and 12-bit (1M
×
SDRAM) address
DRAM Timing: adjustable Trp, Trcd, Tras, and Tcas timings
DRAM Refresh: 1 ~ 8 refresh cycles per scan line
SDRAM Read Latency: 1 ~ 3 clocks
SDRAM Burst Type: sequential or interleaved
SDRAM Burst Length: 1, 2, 4, 8, or full page
SDRAM Self Refresh
Table 7.2 shows the interface signals for SDRAM and EDO DRAM.
Table 7.2 SDRAM and EDO DRAM Interface Signals
Pin Name
256K
′
EDO DRAM
1M
′
EDO DRAM
256K
′
SDRAM
1M
′
SDRAM
MD[15:0]
MD[15:0]
MD[15:0]
MD[15:0]
MD[15:0]
MA[10:0]
MA[8:0]
MA[9:0]
MA[8:0]
MA[10:0]
BA
BA
BA
RAS[1:0]#/CS[1:0]#
RAS[1:0]#
RAS[1:0]#
CS[1:0]#
CS[1:0]#
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