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參數(shù)資料
| 型號： | W9968CF |
| 英文描述： | Digital Camera |
| 中文描述： | 數(shù)碼相機(jī) |
| 文件頁數(shù)： | 39/78頁 |
| 文件大?。?/td> | 814K |
| 代理商： | W9968CF |
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W9968CF
Publication Release Date: May 1999
- 39 - Revision A2
7.8 Microcontroller Interface
The W9968CF supports an external 8-bit microcontroller to access DRAM and W9968CF internal
registers for portable PC camera applications.
7.8.1 Base Address Setup
The W9968CF internal registers occupy 256-byte microcontroller address space. A special base
address (BA) setup mechanism, described as followed, is designed for the microcontroller to configure
base address for the W9968CF internal register access:
1 assert hardware reset.
2 write the key,
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in ASCII code, to the port xx00H.
3 the port address, xx00H, then will be used as Base Address (BA) for the microcontroller
access.
The setup procedure must be executed right after the hardware reset. Once the procedure is finished,
the xx00H address will be used as the base address until another hardware reset is asserted.
7.8.2 W9968CF Register Access
Since all internal registers are 16-bit wide, it takes two cycles for the microcontroller to access one 16-
bit register through the 8-bit data bus. The two microcontroller access cycles should be in low-byte then
high-byte order. For example, to write CR00 register, the microcontroller must write to BA + 00H
address at first, then write to BA + 01H address to complete this 16-bit register access.
7.8.3 Microcontroller Interrupt
The W9968CF interrupts the microcontroller by forcing INT# pin to low when it completes a still image
capture (original video mode) or JPEG compression of this image (JPEG compression mode). Once
interrupt is acknowledged by the microcontroller, it must write one to bit 5 of the Miscellaneous Control
register (CR00_5) to clear the interrupt. Interrupt can also be disabled by writing zero to bit 6 of the
Miscellaneous Control register (CR00_6).
7.8.4 DRAM Access
The external microcontroller can read/write access DRAM through W9968CF by using the following
registers:
uC Access DRAM Start Address Register (BA + 18H ~ 1AH): specifies the 21-bit starting
WORD address of the DRAM to be accessed.
uC Access DRAM Mode Select (bit 8 of BA + 1BH): specifies read or write access mode.
uC Access DRAM Data Port Register (BA + 1CH ~ 1DH): 16-bit data port which stores data
read from DRAM in read mode, or data to be written into DRAM in write mode.
Read Access (uC reads data from DRAM)
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