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參數(shù)資料
| 型號： | W9968CF |
| 英文描述： | Digital Camera |
| 中文描述： | 數(shù)碼相機 |
| 文件頁數(shù)： | 20/78頁 |
| 文件大小： | 814K |
| 代理商： | W9968CF |
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W9968CF
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7 FUNCTIONAL DESCRIPTION
7.1 Video Input Interface
Video input data is cropped, down-scaled, and filtered in the video pre-processing (VPRE) block, then
is stored into the DRAM as captured video for the following JPEG compression and transfer.
7.1.1 Camera Control Serial Bus
A dedicated programmable serial bus is supported for camera control. The serial bus includes SCLK,
SDATA, and SDE#/SDS signals. During serial bus read, these signals are controlled by the host via bits
4-0 of the Serial Bus Control register (CR01_4-0).
There are two serial bus write modes which are controlled by bit 5 of the Serial Bus Control register
(CR01_5).: normal serial bus write mode (CR01_5 = 0) and fast serial bus write mode (CR01_5 = 1).
Normal serial bus write mode (CR01_5 = 0): SDATA and SCLK signals are output from CR01_1-0
directly.
Fast serial bus write mode (CR01_5 = 1): SDATA and SCLK signals are output from CR06-CR09 in
about 400 Khz bit frequency.
7.1.2 Input Video Data Format
The W9968CF accepts video data in YUV 4:2:2 format through a 16-bit (Y[7:0] and UV[7:0]) or 8-bit
(Y[7:0]) data bus. Many YUV ordering formats are supported which are selected by bits 9-8 of the Video
Capture Control register (CR26) as shown in Figure 7.1. Video data can be latched by the W9968CF by
using either rising-edge or falling-edge of the VICLK clock signal. In the 8-bit modes the VICLK
frequency is twice the pixel rate, only Y[7:0] pins are used for video data input and UV[7:0] pins are not
used.
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