
W9968CF
- 46 -
Power-on Default:
0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P7W P6W P5W P4W P3W P2W P1W P0W P7D P6D P5D P4D P3D P2D P1D P0D
Bits 15-8 GPIO[7:0] Direction
0 = Input
1 = Output
Bits 7-0
GPIO[7:0] Data
0 = Low
1 = High
Note. GPIO[7:0] pins are used as A[15:8] to the external microcontroller if used (EXTMCU = 1). This
register does not control on the GPIO[7:0] pins if an external microcontroller is used.
DRAM Timing Control Register (CR03)
Read/Write
Power-on Default:
Index: 0003H
405DH
uC Address: 06H - 07H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Refresh Cycles
DCT
T_RP
RAS
T_RCD
T_RAS
RE
T_CAS
Bit 15
Reserved
Bits 14-12 Refresh Cycles
000 = 1 refresh cycle per horizontal scan line
001 = 2 refresh cycles per horizontal scan line
010 = 3 refresh cycles per horizontal scan line
011 = 4 refresh cycles per horizontal scan line
100 = 5 refresh cycles per horizontal scan line
101 = 6 refresh cycles per horizontal scan line
110 = 7 refresh cycles per horizontal scan line
111 = 8 refresh cycles per horizontal scan line
Bit 11
DCT DRAM Data Access
0 = DCT DRAM data access can be interrupted by MCTL when other DRAM request is
active.
1 = DCT DRAM data access cannot be interrupted by MCTL.