參數(shù)資料
型號： W971GG6IB-25
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84
文件頁數(shù)： 40/86頁
文件大?。?/td> 1360K
代理商： W971GG6IB-25
W971GG6IB
Publication Release Date: Oct. 23, 2009
- 45 -
Revision A02
9.11.2 AC Characteristics and Operating Condition for -25/-3 speed grade
SPEED GRADE
DDR2-800 (-25)
DDR2-667 (-3)
Bin(CL-tRCD-tRP)
5-5-5/6-6-6
5-5-5
SYM.
PARAMETER
MIN.
MAX.
MIN.
MAX.
UNITS25 NOTES
tRCD
Active to Read/Write Command Delay Time
12.5
15
nS
23
tRP
Precharge to Active Command Period
12.5
15
nS
23
tRC
Active to Ref/Active Command Period
52.5
55
nS
23
tRAS
Active to Precharge Command Period
40
70000
40
70000
nS
4,23
tRFC
Auto Refresh to Active/Auto Refresh command
period
127.5
127.5
nS
5
0
°C ≦ TCASE ≦ 85°C
7.8
7.8
μS
5
tREFI
Average periodic
refresh Interval
85
°C
< TCASE ≦ 95°C
3.9
3.9
μS
5,6
tCCD
CAS to CAS command delay
2
2
nCK
tCK(avg) @ CL=3
5
8
5
8
nS
30,31
tCK(avg) @ CL=4
3.75
8
3.75
8
nS
30,31
tCK(avg) @ CL=5
2.5
8
3
8
nS
30,31
tCK(avg)
Average clock period
tCK(avg) @ CL=6
2.5
8
nS
30,31
tCH(avg)
Average clock high pulse width
0.48
0.52
0.48
0.52
tCK(avg)
30,31
tCL(avg)
Average clock low pulse width
0.48
0.52
0.48
0.52
tCK(avg)
30,31
tAC
DQ output access time from CLK/ CLK
-400
400
-450
450
pS
35
tDQSCK
DQS output access time from CLK / CLK
-350
350
-400
400
pS
35
tDQSQ
DQS-DQ skew for DQS & associated DQ signals
200
240
pS
13
tCKE
CKE minimum high and low pulse width
3
3
nCK
7
tRRD
Active to active command period for 2KB page
size
10
10
nS
8,23
tFAW
Four Activate Window for 2KB page size
45
50
nS
23
tWR
Write recovery time
15
15
nS
23
tDAL
Auto-precharge write recovery + precharge time WR + tnRP
WR + tnRP
nCK
24
tWTR
Internal Write to Read command delay
7.5
7.5
nS
9,23
tRTP
Internal Read to Precharge command delay
7.5
7.5
nS
4,23
tIS (base) Address and control input setup time
175
200
pS
10,26,
40,42,43
tIH (base) Address and control input hold time
250
275
pS
11,26,
40,42,43
tIS (ref)
Address and control input setup time
375
400
pS
10,26,
40,42,43
tIH (ref)
Address and control input hold time
375
400
pS
11,26,
40,42,43
tIPW
Address and control input pulse width for each
input
0.6
0.6
tCK(avg)
tDQSS
DQS latching rising transitions to associated
clock edges
-0.25
0.25
-0.25
0.25
tCK(avg)
28
tDSS
DQS falling edge to CLK setup time
0.2
0.2
tCK(avg)
28
tDSH
DQS falling edge hold time from CLK
0.2
0.2
tCK(avg)
28
tDQSH
DQS input high pulse width
0.35
0.35
tCK(avg)
tDQSL
DQS input low pulse width
0.35
0.35
tCK(avg)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W971GG6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM
W971GG6JB-18 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS
W971GG6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA
W971GG6JB25I 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR
W971GG6JB-25I 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY
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