參數(shù)資料
型號(hào)： W971GG6IB-25
廠(chǎng)商： WINBOND ELECTRONICS CORP
元件分類(lèi)： DRAM
英文描述： 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84
文件頁(yè)數(shù)： 17/86頁(yè)
文件大?。?/td> 1360K
代理商： W971GG6IB-25
W971GG6IB
Publication Release Date: Oct. 23, 2009
- 24 -
Revision A02
CMD
12
3
45
6
7
8
9
10
11
12
0
-1
CLK /CLK
DQS/DQS
DQ
AL=2
CL=3
WL=RL-1=4
≧
tRCD
RL=AL+CL=5
Dout0
Din0
Active
A-Bank
Read
A-Bank
Write
A-Bank
Din1
Din2
Din3
Dout1 Dout2 Dout3
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
Figure 14—Example 1: Read followed by a write to the same bank,
where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4
1
2
3
4
56
78
9
10
11
12
0
-1
CL=3
WL=RL-1=2
≧
tRCD
RL=AL+CL=3
AL=0
CMD
CLK/CLK
DQ
Dout0 Dout1 Dout2 Dout3
Din0
Din1
Din2
Din3
Write
A-Bank
Read
A-Bank
Active
A-Bank
DQS/DQS
AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
Figure 15—Example 2: Read followed by a write to the same bank,
where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4
7.4.2
Burst mode operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or
from memory locations (read cycle). The parameters that define how the burst mode will operate are
burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8
bit burst mode, full interleave address ordering is supported, however, sequential address ordering is
nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].
The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless
burst read or write operations are supported.
Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is
prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to
two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms
refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10)
相關(guān)PDF資料
PDF描述
W9751G6JB-25A 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G8JB-18 DDR DRAM, PBGA84
W9812G21H-6I 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
W9812G21H-6C 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86
W9812G6JH-6 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W971GG6JB 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM
W971GG6JB-18 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS
W971GG6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA
W971GG6JB25I 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線(xiàn)串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱(chēng):CAV24C32WE-GT3OSTR
W971GG6JB-25I 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY
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