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參數(shù)資料
| 型號(hào)： | W83977TF(EOL) |
| 英文描述： | W83877TF plus KBC. CIR. RTC |
| 中文描述： | W83877TF加比聯(lián)。稅務(wù)局局長(zhǎng)。時(shí)鐘 |
| 文件頁(yè)數(shù)： | 77/161頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | W83977TF(EOL) |
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W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-68 -
Revision A1
5.2.7 EPP Pin Descriptions
EPP NAME
TYPE
EPP DESCRIPTION
nWrite
O
Denotes an address or data read or write operation.
PD<0:7>
I/O
Bi-directional EPP address and data bus.
Intr
I
Used by peripheral device to interrupt the host.
nWait
I
Inactive to acknowledge that data transfer is completed. Active to
indicate that the device is ready for the next transfer.
PE
I
Paper end; same as SPP mode.
Select
I
Printer selected status; same as SPP mode.
nDStrb
O
This signal is active low. It denotes a data read or write operation.
nError
I
Error; same as SPP mode.
nInits
O
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
nAStrb
O
This signal is active low. It denotes an address read or write operation.
5.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port, and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10
μ
S
have elapsed from the start
of the EPP
cycle to the time
WAIT#
is deasserted. The current EPP
cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
5.2.8.1 EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed asynchronously.
5.2.8.2 EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or
write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds
normally and will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to
active low, at which time it will start as described above.
5.2.8.3 EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive
high.
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