參數(shù)資料
型號: W83977TF(EOL)
英文描述: W83877TF plus KBC. CIR. RTC
中文描述: W83877TF加比聯(lián)。稅務(wù)局局長。時鐘
文件頁數(shù): 64/161頁
文件大?。?/td> 592K
代理商: W83977TF(EOL)
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-55 -
Revision A1
4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR)
Power on default <7:0> = 00000000 binary
Bit
Name
Read/Write
Description
7-3
Reserved
-
Reserved
2
TMR_I
Read Only
Timer Interrupt. Set to 1 when timer count to 0. This bit
will be affected by (1) the timer registers are defined in
Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable
Timer, in Bank0.Reg3.Bit2) should be set to 1, (3)
ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2)
should be set to 1.
1
LSR_I
Read Only
Line-Status-Register interrupt. Set to 1 when overrun,
or time out, or RBR Ready in the Line Status Register
(LSR) sets to 1. Clear to 0 when LSR is read.
0
RXTH_I
Read Only
Receiver Thershold-Level Interrupt. Set to 1 when (1)
the Receiver Buffer Register (RBR) is equal
or
larger
than the threshold level, (2) RBR occurs time-out if the
receiver buffer register has valid data and below the
threshold level. Clear to 0 when RBR is less than
threshold level from reading RBR.
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