參數(shù)資料
型號: W83977TF(EOL)
英文描述: W83877TF plus KBC. CIR. RTC
中文描述: W83877TF加比聯(lián)。稅務(wù)局局長。時鐘
文件頁數(shù): 52/161頁
文件大小: 592K
代理商: W83977TF(EOL)
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-43 -
Revision A1
In the PS/2 Model 30 mode, the bit definitions are as follows:
1
2
3
4
5
6
7
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG#
0
0
0
DSKCHG (Bit 7):
This bit indicates the status of DSKCHG# input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
x
x
x
x
x
x
DRATE0
DRATE1
0
1
2
3
4
5
7
6
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
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