參數(shù)資料
型號(hào)： W83977TF(EOL)
英文描述： W83877TF plus KBC. CIR. RTC
中文描述： W83877TF加比聯(lián)。稅務(wù)局局長。時(shí)鐘
文件頁數(shù)： 114/161頁
文件大?。?/td> 592K
代理商： W83977TF(EOL)
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-105 -
Revision A1
10.4
Logical Device 2 (UART A)
￠)
CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x04 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Serial Port 1.
CRF0 (Default 0x00)
Bit 7 - 2: Reserved.
Bit 1 - 0: SUACLKB1, SUACLKB0
= 00 UART A clock source is 1.8462 Mhz (24MHz/13)
= 01 UART A clock source is 2 Mhz (24MHz/12)
= 10 UART A clock source is 24 Mhz (24MHz/1)
= 11 UART A clock source is 14.769 Mhz (24MHz/1.625)
10.5
CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x03 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Serial Port 2.
Logical Device 3 (UART B)
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