參數(shù)資料
型號: W6692ACD
廠商: WINBOND ELECTRONICS CORP
元件分類: 數(shù)字傳輸電路
英文描述: DATACOM, ISDN CONTROLLER, PQFP100
封裝: LQFP-100
文件頁數(shù): 91/98頁
文件大小: 584K
代理商: W6692ACD
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-91 -
Parameter
Parameter Descriptions
Min.
Nominal
Max.
Remarks
ta1
PBCK pulse high
325
Unit = ns
ta2
PBCK pulse low
195
325
455
ta3
Frame clock asserted from
PBCK
20
ta4
PTXD data delay from PBCK
20
ta5
Frame clock deasserted from
PBCK
20
ta6
PTXD hold time from PBCK
10
ta7
PRXD setup time to PBCK
20
ta8
PRXD hold time from PBCK
10
Note : The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125
s), PBCK and PFCK1,
PFCK2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with S/T clock. This shift is made on the
LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with
jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz.
9.4.2 Serial EEPROM Timing
Parameter
Parameter Descriptions
Min.
Max.
Remarks
tb1
EPSK low
2500
Unit = ns
tb2
EPSK high
2500
tb3
EPCS output delay
30
tb4
EPSD output delay
30
tb5
EPSD tri-state delay
30
tb6
EPSD input setup time
30
tb7
EPSD input hold time
30
A5
A4
A1
A0
.....
D15
D14
D1
D0
.......
tb1 tb2
tb3
tb4
tb5
tb7
tb6
EPSK
EPCS
EPSDI
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