參數(shù)資料
型號： W6692ACD
廠商： WINBOND ELECTRONICS CORP
元件分類： 數(shù)字傳輸電路
英文描述： DATACOM, ISDN CONTROLLER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 17/98頁
文件大?。?/td> 584K
代理商： W6692ACD
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-24 -
A 96 kHz continuous pulse with alternating polarities is sent.
Send Single Pulses
A 2 KHz , isolated pulse with alternating polarities is sent.
Layer 1 Reset
A layer 1 reset command forces the transmission of INFO 0 and disables the S line awake detector. Thus activation from NT
is not possible.
There is no indication in reset state. The reset state can be left only with ECK command.
TABLE 7.2 LAYER 1 COMMAND CODES
Command
Symbol
Code
Description
Enable clock
ECK
0000
Enable internal clocks
Layer 1 reset
RST
0001
Layer 1 reset
Send continuous pulses
SCP
0100
Send continuous pulses at 96 kHz
Send single pulses
SSP
0010
Send isolated pulses at 2 kHz
Activate request at priority 8
AR8
1000
Activate layer 1 and set D channel priority level to 8
Activate request at priority 10
AR10
1001
Activate layer 1 and set D channel priority to 10
Enable analog loopback
EAL
1010
Enable analog loopback
Deactivate layer 1
DRC
1111
Deactivate layer 1 and disable internal clocks
TABLE 7.3 LAYER 1 INDICATION CODES
Indication
Symbol
Code
Descriptions
Clock Enabled
CE
0111
Internal clocks are enabled
Deactivate request downstream
DRD
0000
Deactivation request by S interface, i.e INFO 0 received
Level detected
LD
0100
Signal received, receiver not synchronous
Activate request downstream
ARD
1000
INFO 2 received
Test indication
TI
1010
Analog loopback activated or continuous zeros or single zeros
transmitted
Awake test indication
ATI
1011
Level detected during test function
Activate indication with priority
class 1
AI8
1100
INFO 4 received, D channel priority is 8 or 9
Activate indication with priority
class 2
AI10
1101
INFO 4 received, D channel priority is 10 or 11
Clock disabled
CD
1111
Layer 1 deactivated, internal clocks are disabled
7.2.3.2 State Transition Diagrams
The followings are the state transition diagrams, which implement the activation/deactivation state matrix in I.430 (TABLE
5/I.430). The "command" and "s receive" entries in each state octagon keep the state, the "indication" and "s transmit" entries in
each state octagon are the state outputs. For example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the
command is "ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the microprocessor
and transmits INFO 0 on S interface. The "AR8/10" command causes transition to F4 and non-INFO 0 signal causes transition to
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