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參數(shù)資料
| 型號： | W6692ACD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁數(shù)： | 35/98頁 |
| 文件大?。?/td> | 584K |
| 代理商： | W6692ACD |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-40 -
During the frame transmission, the microprocessor reaction time for the XFR interrupt depends on the FIFO threshold setting
and B channel data rate. For example, it is 8 ms if the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the
microprocessor fails to responds within the given reaction time, the transmit FIFO will be underrun. In this case, the W6692A
will automatically reset the transmitter and send the inter frame time fill pattern on B channel. The microprocessor is informed
about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The microprocessor must wait until
transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
The microprocessor can abort a frame transmission by issuing a Transmitter Reset command (XRES bit in Bn_CMDR
register). The XRES command resets the transmitter and sends inter frame time fill pattern on B channel. It also results in a
transmit pool ready condition.
Extended transparent mode:
All the data in the transmit FIFO are transmitted without any modification, i.e. no flags and CRCs are inserted, and no bit
stuffing is performed.
Transmission is started by a XMS command. The transmitter requests another block of data via XFR interrupt when more
than a threshold length of vacancies are left in the FIFO. The microprocessor reacts to this condition by writing up to a threshold
length of data into the transmit FIFO and issues a XMS command to continue the message transmission.
The microprocessor reaction time depends on the FIFO threshold setting and B channel data rate. For example, it is 8 ms if
the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the microprocessor fails to respond within the given reaction
time, the transmit FIFO will hold no data to transmit. In this case, the W6692A will automatically reset the transmitter and send
idle channel pattern defined in Bn_IDLE register. The microprocessor is informed about this via a Transmit Data Underrun
interrupt (XDUN bit in Bn_EXIR register). The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-
write data, and issue XMS command to re-transmit the data.
7.8 GCI Mode Serial Interface Bus
The GCI is a generalization and enchancement of the general purpose, serial interface bus. The channel structure of the GCI
mode is depicted below. The timing is compatible with Siemens’s IOM-2 TE mode.
Channel Structure of the W6692A GCI Mode:
FSC
CH0
CH1
CH2
B1
B2
MON0
D
C/I0
IC1
IC2
MON1
C/I1
C/I2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W6692ACF | DATACOM, ISDN CONTROLLER, PQFP100 |
| W6694ACD | DATACOM, ISDN CONTROLLER, PQFP48 |
| W671320P | TELECOM-SLIC, PQCC28 |
| W671361P | TELECOM-SLIC, PQCC28 |
| W671361Y | TELECOM-SLIC, QCC32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W66ARX-18 | 制造商:Magnecraft 功能描述: |
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