參數(shù)資料
型號(hào): W6692ACD
廠商: WINBOND ELECTRONICS CORP
元件分類: 數(shù)字傳輸電路
英文描述: DATACOM, ISDN CONTROLLER, PQFP100
封裝: LQFP-100
文件頁數(shù): 72/98頁
文件大?。?/td> 584K
代理商: W6692ACD
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-74 -
RMR
Receive Message Ready
At least a
threshold lenth of data has been stored in the B1_RFIFO.
RME
Receive Message End
Used in transparent mode only. The last block of a frame has been received. The frame length can be found in B1_RBCH +
B1_RBCL registers. The number of data available in the B1_RFIFO equals frame lenth modulus threshold. The result of CRC
check is indicated by B1_STAR:CRCE bit.
When the number of last block of a frame equals the threshold, only RME interrupt is generated.
RDOV
Receive Data Overflow
Data overflow occurs in the receive FIFO. The incoming data will overwrite the data in the receive FIFO.
XFR
Transmit FIFO Ready
This interrupt indicates that up to a threshold length of data can be written into the B1_XFIFO.
XDUN
Transmit Data Underrun
This interrupt occurs when the B1_XFIFO has run out of data. In this case, the W6692A will automatically reset the
transmitter and send the inter frame time fill pattern on B channel. The software must wait until transmit FIFO ready condition
(via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
8.2.6 B1_ch Extended Interrupt Mask Register
B1_EXIM
Read/Write
Address 94H/25H
Value after reset: FFH
7
6
5
4
3
2
1
0
RMR
RME
RDOV
XFR
XDUN
Setting the bit to "1" masks the corresponding interrupt source in B1_EXIR register. Masked interrupt status bits are read as
zero when B1_EXIR register is read. They are internally stored and pending until the mask bits are zero.
All the interrupts in B1_EXIR will be masked if the IMASK : B1_EXI bit is set to "1".
8.2.7 B1_ch Status Register B1_STAR
Read
Address 98H/26H
Value after reset: 20H
7
6
5
4
3
2
1
0
RDOV
CRCE
RMB
XDOW
XBZ
RDOV
Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The overflow
condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data
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