參數(shù)資料
型號: VG36641641BT
廠商: Vanguard International Semiconductor Corporation
英文描述: CMOS Synchronous Dynamic RAM
中文描述: 同步動態(tài)隨機存儲器的CMOS
文件頁數(shù): 8/69頁
文件大小: 1364K
代理商: VG36641641BT
Document :1G5-0177
Rev.2
Page 8
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, V
DD
= V
DDQ
= 3.3
0.3V , V
SS
= V
SSQ
= 0V, unless otherwise noted)
Notes
1. -6 grade is available only on 4MX16 option.
2. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Parameter
Sym-
bol
Limits
Unit
Note
-6
*1
-7
-7L
-8H
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CL = 3
t
CK3
t
CK2
t
AC3
t
AC2
t
CH
t
CL
t
CKS
t
CKH
t
AS
t
AH
t
CMS
t
CMH
t
DS
t
DH
t
OH3
t
OH2
t
LZ
t
HZ
t
RC
t
RAS
t
RCD
t
RP
t
RRD
t
DPL
t
T
t
RSC
t
REF
6
7
7.5
8
ns
CL = 2
7.5
7.5
10
10
ns
CLK to valid output
delay
CL = 3
5
5.4
5.4
6
ns
*2
CL = 2
6
6
6
6
ns
*2
CLK high pulse width
2.5
2.5
2.5
3
ns
CLK low pulse width
2.5
2.5
2.5
3
ns
CKE setup time
1.5
1.5
1.5
2
ns
CKE hold time
0.8
0.8
0.8
1
ns
Address setup time
1.5
1.5
1.5
2
ns
Address hold time
0.8
0.8
0.8
1
ns
Command setup time
1.5
1.5
1.5
2
ns
Command hold time
0.8
0.8
0.8
1
ns
Data input setup time
1.5
1.5
1.5
2
ns
Data input hold time
0.8
0.8
0.8
1
ns
Output data hold
time
CL = 3
2.5
2.7
2.7
3
ns
*2
CL = 2
2.5
2.7
3
3
ns
*2
CLK to output in low - Z
0
0
0
0
ns
CLK to output in H - Z
2.5
5
2.7
5.4
2.7
5.4
3
6
ns
ROW cycle time
60
63
67.5
70
ns
ROW active time
42
100K
42
100K
45
100K
50
100K
ns
RAS to CAS delay
18
20
20
20
ns
Row precharge time
15
15
20
20
ns
Row active to active delay
12
14
15
20
ns
Data in to precharge
12
14
15
20
ns
Transition time
1
10
1
10
1
10
1
10
ns
Mode reg. set cycle
2
2
2
2
tck
Refresh time
64
64
64
64
ms
±
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