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參數資料
| 型號： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數： | 79/79頁 |
| 文件大?。?/td> | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of
EMRS.
13. The DDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
Programming the Mode Register
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR)
are user defined variables and must be programmed with a Mode Register Set (MRS) command. Addition-
ally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended
strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be pro-
grammed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or
Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the
user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when
the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be
executed any time after power-up without affecting array contents.
Initialization Sequence af ter Power Up
/CK
CK
CKE
Command
PRE
ALL
PRE
ALL
EMRS
MRS
REF
MRS
EMRS
ANY
CMD
DLL
ENABLE
DLL
RESET
OCD
Default
OCD
CAL. MODE
EXIT
Follow OCD
Flowchart
400ns
tRFC
tRP
tMRD
tOIT
min. 200 Cycle
NOP
ODT
tCL
tCH
tIS
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