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參數(shù)資料
| 型號(hào)： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 74/79頁 |
| 文件大小： | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Reference Loads, Slew Rates and Slew Rate Derating
Reference Load for Timing Measurements
The figure represents the timing reference load used in defining the relevant timing parameters of the device.
It is not intended to either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to cor-
relate the timing reference load to a system environment. This load circuit is also used for output slew rate
measurements.
25 Ohm
Vtt = VDDQ / 2
CK, CK
DUT
Timing Reference Points
VDDQ
DQ
DQS
RDQS
Note: The output timing reference voltage level for single ended signals is the crosspoint with VTT.
The output timing reference voltage level for differential signals is the crosspoint of the
true (e.g. DQS) and the complement (e.g. DQS) signal.
Slew Rate Measurements
Output Slew Rate
Output slew rate is characterized under the test conditions as shown in the figure below
25 Ohm
Vtt = VDDQ / 2
DUT
Test Point
VDDQ
DQ
DQS
RDQS
Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single
ended signals.For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS =
- 500 mV and DQS - DQS = + 500 mV.Output slew rate is guaranteed by design, but is not necessarilty tested
on each device.
Input Slew Rate
Input slew for single ended signals is measured from dc-level to ac-level from VREF to VIH(AC),min for rising
and from VREF to VIL(AC), min or falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
CK -CK = +500 mV (250 mV to -500 mV for falling edges). Test conditions are the same as for timing mea-
surements.
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