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參數(shù)資料
| 型號： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 49/79頁 |
| 文件大小： | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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53
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The pur-
pose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands
between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held
high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command
occurs when CS is brought high, the RAS, CAS, and WE signals become don’t care.
Input Clock Frequency Change
During operation the DRAM input clock frequency can be changed under the following conditions:
a) During Self-Refresh operation
b) DRAM is in precharged power-down mode and ODT is completely turned off.
The DDR2-SDRAM has to be in precharged power-down mode and idle. ODT must be allready turned off and
CKE must be at a logic “l(fā)ow” state. After a minimum of two clock cycles after tRP and tAOFD have been sat-
isfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before
CKE can be changed to a “high” logic level again. After tXP has been satisfied a DLL RESET command via
EMRS has to be issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off.
After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency.
CK
CKE
T0
T4
Tx+1
Ty
Ty+1
Ty+2
T1
T2
Tx
CK
Valid
DLL
NOP
200 Clocks
Frequency Change
Ty+3
Tz
NOP
RESET
tRP
Clock Frequency Change in Precharge Power Down Mode
tXP
Occurs here
tAOFD
Stable new clock
before power down exit
ODT is off during
DLL RESET
Minmum 2 clocks
required before
changing frequency
ODT
RAS, CS
CAS, WE
Ty+4
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