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參數(shù)資料
| 型號： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 7/79頁 |
| 文件大小： | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are
driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In
Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS (and RDQS) signals are driven
low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS (and RDQS) signals are
driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default,
output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and
voltage conditions. Output driver characteristics for OCD calibration default are specified in the following
table. OCD applies only to normal full strength output drive setting defined by EMRS and if half strength is
set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD
default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is
set to default, subsequent EMRS commands not intended to adjust OCD characteristics must specify A7~A9
as ’000’ in order to maintain the default or calibrated value.
Off- Chip-Driver program
A9
A8
A7
Operation
0
OCD calibration mode exit
0
1
Drive(1) DQ, DQS, (RDQS) high and DQS, (RDQS) low
0
1
0
Drive(0) DQ, DQS, (RDQS) low and DQS, (RDQS) high
1
0
Adjust mode
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4 bit
burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4
via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same
time. DT0 is the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output imped-
ance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given
DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment
is 8 and when the limit is reached, further increment or decrement code has no effect. The default setting may
be any step within the 8 step range.
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