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參數資料
| 型號： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數： | 43/79頁 |
| 文件大小： | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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48
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Refresh
SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two
ways : by an explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing
the number of device rows into the rolling 64 ms interval defined the average refresh interval tREFI, which is
a guideline to controlles for distributed refresh timing. For example, a 512Mbit DDR2 SDRAM has 8192 rows
resulting in a tREFI of 7,8 s.
Auto-Refresh Command
Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it
must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh
controller. This makes the address bits ”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM
requires Auto-Refresh cycles at an average periodic interval of tREFI (maximum).
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-
Refresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time
(tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses
during the refresh cycle. No control of the external address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay
between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Com-
mand must be greater than or equal to the Auto-Refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2
SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next
Auto-Refresh command is 9 * tREFI.
T0
T2
T1
T3
AR
CK, CK
CMD
Precharge
> = t
RP
NOP
AUTO
REFRESH
ANY
NOP
> = t
RFC
> = t
RFC
AUTO
REFRESH
NOP
CKE
"high"
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