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參數(shù)資料
| 型號： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 40/79頁 |
| 文件大小： | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The
DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the
write recovery time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank
undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two con-
ditions are satisfied.
(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
In DDR2 SDRAMs the write recovery time delay (WR ) has to be programmed into the MRS mode register.
As long as the analog tWR timing parameter is not violated, WR can be programmed between 2 and 6 clock
cycles. Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL.
Examples:
Burst Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4
NOP
Bank A
Activate
NOP
WRITE A
T0
T2
T1
T3
T4
T5
T6
T7
NOP
CMD
DQ
BW-AP223
A10 ="high"
tRP
Auto-Precharge Begins
DIN A0 DIN A1 DIN A2 DIN A3
WL = RL-1 = 2
WR
tRCmin.
DQS,
DQS
Completion of the Burst Write
tDAL
>=tRASmin.
CK, CK
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| V59C1G01408QAJ37I | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
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