參數(shù)資料
型號(hào)： V59C1G01408QAJ37E
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 256M X 4 DDR DRAM, 0.5 ns, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù)： 20/79頁(yè)
文件大?。?/td> 1029K
代理商： V59C1G01408QAJ37E
27
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst
sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for
ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the
MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3)
of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write oper-
ation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when
burst length = 8 is used, see the “Burst Interruption “ section of this datasheet. A Burst Stop command is not
supported on DDR2 SDRAM devices.
Burst Length and Sequence
gq
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
4
x 0 0
0, 1, 2, 3
x 0 1
1, 2, 3, 0
1, 0, 3, 2
x 1 0
2, 3, 0, 1
x 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Note: 1) Page length is a function of I/O organization
128Mb X 4 organization (CA0-CA9, CA11); Page Length = 1 kByte
64Mb X 8 organization (CA0-CA9 ); Page Length = 1 kByte
32Mb X 16 organization (CA0-CA9); Page Length = 2 kByte
2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR
or DDR components
相關(guān)PDF資料
PDF描述
V59C1G01408QAJ37I 256M X 4 DDR DRAM, 0.5 ns, PBGA68
V5D010EB4D SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.5A, 125VDC, 4.4mm, PANEL MOUNT
V5F110CB SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, PANEL MOUNT
V5PNF CABLE TERMINATED, FEMALE, N CONNECTOR, THREAD-IN STUB SELF-FLARE
V5T110TB3 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.6A, 125VDC, 2.4mm, PANEL MOUNT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V5A010CB 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER
V5A010CB 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER
V5A010CB4D 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
V5A010CB4D 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
V5A010CB4E 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*