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參數(shù)資料
| 型號(hào)： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 28/79頁 |
| 文件大小： | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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34
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Write Data Mask
One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for
x16 components are supported on DDR2 SDRAMs, consistent with the implementation on DDR SDRAMs. It
has identical timings on write operations as the data bits, and though used in a uni-directional manner, is
internally loaded identically to data bits to insure matched system timing. Data mask is not used during read
cycles. If DM is high during a write burst coincident with the write data, the write data bit is not written to the
memory. For x8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS.
.
Write Data Mask Timing
DQS,
DQS
t DQSH
tDQSL
t WPRE
WPST
t
DQ
Din
tDS
DH
DM
don’t care
Din
t
.
Burst Write Operation with Data Mask : RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3 , BL = 4
NOP
WRITE A
T0
T2
T1
T3
T4
T5
T6
T7
Tn
WL = RL-1 = 2
DM
CMD
DQ
NOP
tWR
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
DM
DIN A0
DIN A3
CK, CK
DIN A1 DIN A2
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