參數(shù)資料
型號: UPD61051
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER
中文描述: 馬鞍山集成電路MPEG2音頻/視頻編碼器
文件頁數(shù): 49/106頁
文件大小: 824K
代理商: UPD61051
Data Sheet S15082EJ4V0DS
49
μ
PD61051, 61052
3.2.8
ROM access cycle register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
35H
iROM2 to iROM0
R/W
Mask ROM cycle
It specifies the access cycle of the instruction ROM of internal CPU when connecting host CPU interface with the
serial bus. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 7H.
Bit
Field
Function
Initial value
7 to 3
Reserved (Set 0)
2 to 0
iROM2 to
iROM0
Access cycle of instruction ROM
0: Reserved, 1 to 7: (Setting value+2) by 24.6 MHz
7H
3.2.9
Port setup register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
36H
ISREQ
OSVLD
R/W
Port setup
This register sets the active polarity of ISREQ and OSVLD. The reset of the RESET pin or ALL RESET of the
reset register initializes this address to 0H.
Bit
Field
Function
Initial value
7 to 2
Reserved (Set 0)
1
ISREQ
Active polarity of ISREQ
0: Low active of request, 1: High active of request
0
0
OSVLD
Active polarity of OSVLD/OSRDY
0: Low active of valid/ready
1: High active of valid/ready
0
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