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參數(shù)資料
| 型號： | UPD61051 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數(shù)： | 46/106頁 |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61051 |
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Data Sheet S15082EJ4V0DS
46
μ
PD61051, 61052
SDRAM write
<1> Interrupt mask
Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer.
<2> Set destination address
Host CPU sets the address of SDRAM to the destination address register (24H to 26H) of the
μ
PD61051/61052.
<3> Set the number of the data to write by a 4 byte unit
Host CPU sets the data number of the bytes by 4 bytes unit to the transfer data counter register (27H to 29H) of
the
μ
PD61051/61052.
<4> Set the transfer of host CPU
→
SDRAM
Host CPU sets 02H to the transfer mode register (20H) of the
μ
PD61051/61052.
<5> Data write
Host CPU writes data to the transfer data register (3FH) of the
μ
PD61051/61052 at times with more few 128 bytes
or transfer data count register setting value.
<6> CINT interrupt (Interrupt pin)
<7> Confirm the interrupt factor
When the number of the transfer data is less then 128 bytes, host CPU confirms that the interrupt register 0 (30H)
of the
μ
PD61051/61052 becomes 01H, and go to <9>.
<8> Confirm that next data transfer prepare completed
Host CPU confirms that the interrupt register 0 (30H) of the
μ
PD61051/61052 becomes 02H or 01H and clears a
writing sane value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the
μ
PD61051/61052.
Return to <5> and next data write.
<9> Release of SDRAM
→
host CPU
Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the
μ
PD61051/61052
after setting 00H to the transfer mode register (20H) of the
μ
PD61051/61052.
<10> Release of interrupt mask
It releases the limitation on interrupt which is set by <1>.
<11> In the case of an interrupt to internal CPU, it is necessary
Host CPU sets a data bank number and the number of the bytes to the address that defined with the firmware.
It sets 01H to the 2AH address of the
μ
PD61051/61052 and it notifies an interrupt to internal CPU.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UPD61051GD-LML | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD61051GD-LML-A | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD61052 | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD61052GD-LML | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD61052GD-LML-A | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
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