
Data Sheet S15082EJ4V0DS
17
μ
PD61051, 61052
2.1.3
(1)
Video input
The video input format is ITU-R BT.656 (8-bit Y/Cb/Cr the 4:2:2 format) and 8-bit Y/Cb/Cr which deals with the
4:2:0 format. The horizontal synchronization signal, the vertical synchronization signal and the field index can be
used without using SAV and EAV. In this case, IVFLD can be used by taking with IVVSYNC or it judges a field
judgment in the polarity of IVHSYNC behind the falling edge two clock of IVVSYNC. It judges that an odd field is
'H' and an even field is 'L'. IVVSYNC and IVHSYNC need the high / low period more than 3 IVCLK. The
video-input unit watches over the synchronization signals and detects synchronous error.
(2)
Picture size conversion filter
For adapting to the bit rate of the stream, the picture size of the encoding can be changed. In addition, picture
size changed with the external filter to the 4:2:0 format can be inputted directly, too.
Table 2-2. Input Video Data Arrangement
Input/output processing
Format
Line
Data arrangement
4:2:2
Odd/even lines
Cb0, Y0, Cr0, Y1, Cb1, Y2, Cr1, Y3, Cb2, Y4, Cr2, Y5, …
4:2:0
Odd lines
Cb0, Y0, Cr0, Y1, Cb1, Y2, Cr1, Y3, Cb2, Y4, Cr2, Y5, …
Even lines
(-), Y0, (-), Y1, (-), Y2, (-), Y3, (-), Y4, (-), Y5, …
(3)
Time base corrector (TBC)
It has a frame-type TBC. It is possible to make stable encoding of the channel changing and the nonstandard
video signal such as VTR. When using TBC, it needs over 64 Mbits SDRAM. The following video signals can be
corrected.
Table 2-3. Correctable Video Signals
Horizontal Sync
Vertical Sync
NTSC
1626 to 1806 IVCLK/H
246 to 278 H/V
PAL
1628 to 1828 IVCLK/H
294 to 330 H/V
Remark
IVCLK: 27 MHz
(4)
Noise reduction
Respectively the noise reduction of the luminance signal and the color signal can be set three levels
(5)
Slicer
Slicer decodes the luminance signal to the vertical blanking data. It detects VBID, Closed Caption, and Wide
Screen Signal. The host CPU can read, and stop encoding and re-write the copy control information in VBID and
the Wide Screen Signal, on the host CPU interface.