參數(shù)資料
型號: UPD61051
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER
中文描述: 馬鞍山集成電路MPEG2音頻/視頻編碼器
文件頁數(shù): 38/106頁
文件大小: 824K
代理商: UPD61051
Data Sheet S15082EJ4V0DS
38
μ
PD61051, 61052
3.
SYSTEM INTERFACE REGISTER
This LSI corresponds to the various operation modes in exchange instruction of internal CPU from SDRAM to
instruction RAM (iRAM).
This has 64 byte Registers. They are defined to common registers, interrupt registers and interrupt mask registers.
When there is access in the same address from both of the internal CPU and the host CPU, the later data is left at the
register.
Also, when the writing occurs to the same address at the same time about the common register, the data of the
host CPU is left at the register
Figure 3-1. System Interface Register
Host
CPU
System
Interface
Register
Instruction
RAM of
Internal CPU
Internal
CPU
SDRAM
Interface
SDRAM
DMA
Controller
μPD61051/61052
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