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參數(shù)資料
| 型號： | TTSI2K32T |
| 廠商： | Lineage Power |
| 英文描述： | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機(jī)) |
| 中文描述： | 2048通道，32道時隙交換器（2048通道，32路干線時隙交換機(jī)） |
| 文件頁數(shù)： | 54/66頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TTSI2K32T |
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TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
54
Lucent Technologies Inc.
Connection Store Memory
(continued)
TSDSM[5—0] (bits 7—5) of byte 1 of the connection store select the source of data for each of the time slots being
transmitted by the TTSI2K32T. The configuration can be divided into three groups.
Group 1
Low-Latency Mode.
For the time slots marked as low latency, the transmit data will be retrieved from
the data store based on the programming of TSA[6—0] (bits 6—0) of byte 0 and RXHWY[4—0]
(bits 4—0) of byte 1. Bit 7 of byte 0 is ignored. When each of the individual transmit time slots are
retrieved from the data store memory for transmission, the most recent copy of the receive time slot will
be fetched resulting in a latency that never exceeds 134
μ
s. This is the maximum latency for low-
latency mode independent of highway configurations (e.g., highway speed, clock speed, offsets, etc.).
Refer to the Low-Latency and Frame-Integrity Modes section on page 25 for a detailed description of
the latency calculation.
Frame-Integrity Mode.
For the time slots marked as frame integrity, the transmit data will be retrieved
from the data store based on the programming of TSA[6—0] (bits 6—0) of byte 0 and RXHWY[4—0]
(bits 4—0) of byte 1. Bit 7 of byte 0 is ignored. Any number of time slots from any number of transmit
highways can be marked for frame integrity. When each of the individual transmit time slots marked for
frame integrity are retrieved from the data-store memory for transmission, the internal controller
ensures that they are chosen from a receive frame which has already been entirely stored in the data
store, thereby ensuring frame integrity.
Refer to the Low-Latency and Frame-Integrity Modes section on page 25 for a detailed description of
the actual latency incurred through the device.
Group 2
Host-Data Substitution Mode.
This mode also provides the means to transmit host-supplied data
repeatedly onto any or all of the 2048 transmit time slots; however, the data to be substituted is stored
in HSD[7—0] (bits 7—0) of byte 0 for each transmit time slot. RXHWY[4—0] (bits 4—0) of byte 1 are
ignored in this mode. Host-data mode can be used to customize the data for each of the 2048 transmit
time slots. When a time slot is configured for host-data substitution mode, the data written to byte 0 of
the connection store will have the following convention. Bit 7 is first transmitted, and bit 0 is last trans-
mitted.
Idle-Code Substitution Mode.
These three idle-code substitution modes provide the means to trans-
mit microprocessor data repeatedly onto any or all of the 2048 transmit time slots. Three idle-code reg-
isters (separate from the connection store memory) provide the capability to repeatedly broadcast three
different programmed values to any or all time slots set for idle-code substitution mode. When program-
ming idle-code substitution mode, only the TSDSM[2—0] (bits 7—5) of byte 1 for all of the transmit time
slots involved needs to be written. Byte 0 and RXHWY[4—0] (bits 4—0) of byte 1 are both ignored.
Test-Pattern Substitution Mode.
This mode is also used to substitute alternative transmit data rather
than use the receive time slots being stored in the data store. Since the test-pattern selection is done
outside of the connection store, only TSDSM[2—0] (bits 7—5) of byte 1 for each of the time slots
involved needs to be programmed. Byte 0 and RXHWY[4—0] (bits 4—0) of byte 1 are both ignored.
The test-pattern selection and usage rules are described in the Test-Pattern Generation section on
page 29.
Group 3
High-Impedance Mode.
This mode is used to 3-state any of the 2048 transmit time slots on an individ-
ual basis. For example, consider the case where an 8.192 Mbits/s highway is shared by four devices,
each having one-fourth of the total bandwidth. If the TTSI2K32T were allocated time slots 64—95, then
high-impedance mode would be set for time slots 0—63 and 96—127. Time slots 64—95 could be set
to any combination of the eight possible modes. When programming the high-impedance mode, only
TSDSM[2—0] (bits 7—5) of byte 1 for all of the transmit time slots involved needs to be written. Con-
nection store byte 0 and RXHWY[4—0] (bits 4—0) of byte 1 are both ignored.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
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