參數(shù)資料
型號: TTSI2K32T
廠商: Lineage Power
英文描述: 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時(shí)隙交換機(jī))
中文描述: 2048通道,32道時(shí)隙交換器(2048通道,32路干線時(shí)隙交換機(jī))
文件頁數(shù): 18/66頁
文件大?。?/td> 1321K
代理商: TTSI2K32T
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
18
Lucent Technologies Inc.
Microprocessor Interface
The host interface is designed to connect directly to a typical synchronous or asynchronous host bus. The interface
to the TTSI2K32T includes a separate clock, PCLK, which is used only in the synchronous interface mode. This
device will be a slave on the host bus and will provide the host microprocessor with the capability to read and write
the TTSI2K32T address space in a minimal number of clock cycles. There is no posting of writes in the host inter-
face, and all registers and the data and connection stores are directly accessible.
Asynchronous Mode (MM = 0)
The following two timing diagrams show read and write in the asynchronous mode.
5-6954(F).r3
Figure 5. Asynchronous Read
5-6955(F)r.3
Figure 6. Asynchronous Write
The presence of AS, CS, and DS being asserted will start the TTSI2K32T internal access. Once data has been
retrieved or written, DT will be asserted indicating the TTSI2K32T is ready to terminate the access. DT will continue
to be asserted until AS, CS, or DS is negated.
The duration of an asynchronous read or write cycle will be a maximum of 183 ns. This duration is measured from
when AS, CS, and DS are all asserted low until DT is asserted low by the TTSI2K32T.
READ DATA
TSI READ ADDRESS
D[7—0]
A[14—0]
CS
AS
R/W
DS
DT
HIGH IMPEDANCE
183 ns MAX
TSI WRITE DATA
TSI WRITE ADDRESS
D[7—0]
A[14—0]
CS
AS
R/W
DS
DT
HIGH IMPEDANCE
183 ns MAX
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