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參數(shù)資料
| 型號： | TTSI2K32T |
| 廠商： | Lineage Power |
| 英文描述： | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
| 中文描述： | 2048通道，32道時隙交換器（2048通道，32路干線時隙交換機） |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TTSI2K32T |
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TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
40
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 18. Idle Code 1 Register (0x03)
Table 19. Idle Code 2 Register (0x04)
Table 20. Idle Code 3 Register (0x05)
Table 21. Global Interrupt Mask Register (0x06)
Bit
7—0
Symbol
IC1
Name/Description
Idle Code 1[7
—
0].
This register is used to identify the data to be sent on any
outgoing time slot marked for idle code 1 transmission. Idle code transmission is
enabled via the time-slot data select mode bits. See Table 45, Connection Store
Memory (Byte 1), on page 53.
Bit
7—0
Symbol
IC2
Name/Description
Idle Code 2[7
—
0].
This register is used to identify the data to be sent on any
outgoing time slot marked for idle code 2 transmission. Idle code transmission is
enabled via the time-slot data select mode bits. See Table 45, Connection Store
Memory (Byte 1), on page 53.
Bit
7—0
Symbol
IC3
Name/Description
Idle Code 3[7
—
0].
This register is used to identify the data to be sent on any
outgoing time slot marked for idle code 3 transmission. Idle code transmission is
enabled via the time-slot data select mode bits. See Table 45, Connection Store
Memory (Byte 1), on page 53.
Bit
7—1
0
Symbol
—
GIE
Name/Description
Reserved.
Read as 0.
Global Interrupt Enable.
This bit must be written to a 1 in order for INT to be
asserted as a result of the possible interrupt conditions. This is in addition to
the mask bits in the interrupt mask register. When 0, the INT output is blocked
independent of the programming of the interrupt mask register. When 1, the
INT output is enabled and will be asserted based on the interrupt status and
mask bits.
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