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參數(shù)資料
| 型號： | TTSI2K32T |
| 廠商： | Lineage Power |
| 英文描述： | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
| 中文描述： | 2048通道，32道時隙交換器（2048通道，32路干線時隙交換機） |
| 文件頁數(shù)： | 30/66頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TTSI2K32T |
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TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
30
Lucent Technologies Inc.
Test-Pattern Checking
(continued)
2.
Set the Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 27 on page 45 and the Test-Pattern
Checker Lower Time-Slot Register (0x0D), Table 28 on page 45 to indicate the range of input time slots which
will be carrying test data. The range is inclusive of the time slots indicated in both registers. If only one time slot
is to be selected, then the upper and lower registers should be set to the same value.
Set CPS[3—0] (bits 3—0) of the Test-Pattern Style Register (0x0A), Table 25 on page 44 to select the test pat-
tern to detect. If a fixed, user-defined byte is to be detected, the CTP[7—0] bits in the Test-Pattern Checker
Data Register (0x0E), Table 29 on page 45 should also be programmed with the user-defined pattern.
Select the data rate of the test-pattern checker via CHKHDR[1—0] (bits 3—2) and set STTPC (bit 6) in the Test
Command Register (0x09), Table 24 on page 43 to prompt the checker to attempt to lock onto the selected
test-pattern style.
If there is a need to restart the checker (i.e., the test-pattern style has changed), then STTPC (bit 6) of the Test
Command Register (0x09), Table 24 on page 43 must first be cleared to 0, and then steps 3 and 4 should be
repeated.
3.
4.
There is an interrupt register status bit related to the test-pattern checker. TPD (bit 5) of the Interrupt Status Regis-
ter (0x07), Table 22 on page 41 is used to determine when, if ever, the pattern is detected. The TPD interrupt status
bit will remain 0 until the pattern has been detected. This bit is cleared when read. Once TPD is set, it will not be set
again until the checker is instructed to relock on the test pattern by clearing and then setting STTPC (bit 6) in the
test command register.
Error Injection
The error injection feature provides the capability to inject errors into the outgoing test-pattern data. The number of
errors injected is set using the Test-Pattern Error Injection Register (0x0F), Table 30 on page 45.
If error injection is required, the process should start by setting up the test-pattern generator using steps 1—3 in
the Test-Pattern Generation section on page 29. In order to start injecting errors into the outgoing test pattern, write
the Test-Pattern Error Injection Register (0x0F), Table 30 on page 45 with the number of errors desired. When all of
the errors have been injected into the outgoing data stream, the interrupt status bit BEI (bit 0) will be set in the
Interrupt Status Register (0x07), Table 22 on page 41. Errors will be injected at the rate of one per time slot. Test
Command Register (0x09), Table 24 on page 43 will be cleared to 0 when BEI is set.
Error Checking
Errors are checked on time slots marked for test-pattern data once the checker has locked onto the test pattern.
Every time an error is detected, the ERD (bit 3) interrupt status bit is set and the test-pattern error counter register
contents are incremented. There are two registers Test-Pattern Error Counter (Byte 0) (0x10), Table 31 on page 46
and Test-Pattern Error Counter (Byte 1) (0x11), Table 32 on page 46, that are used to track the number of errors
detected on incoming test patterns.
The error counter registers are reset after both have been read. In order to ensure that the correct value is read
from these registers, byte 0 must be read first followed by byte 1. This action will latch the counter value and allow
the counter logic to be reset and then continue recording.
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相關(guān)代理商/技術(shù)參數(shù) |
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