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參數(shù)資料
| 型號： | TTSI2K32T |
| 廠商： | Lineage Power |
| 英文描述： | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
| 中文描述： | 2048通道，32道時隙交換器（2048通道，32路干線時隙交換機） |
| 文件頁數(shù)： | 39/66頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TTSI2K32T |
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Preliminary Data Sheet
February 1999
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
39
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 16. Software Reset Register (0x01)
Table 17. BIST Command Register (0x02)
The BIST test sequence is performed as follows:
1.
2.
Set RB (bit 7) in the BIST command register to 1 in order to initiate the internal BIST test.
Wait for the BIST complete (BC) (bit 1 of the interrupt status register) interrupt to occur via the interrupt status
register, if it is not masked via the interrupt mask register MASKBC bit (bit 1). Alternatively, the host can poll
the BD bit in the BIST command register which will also indicate the completion of BIST.
Once the BIST interrupt occurs or the BD bit is set, the BPF bit in the BIST command register will reflect the
BIST pass/fail result. A BPF set to 0 indicates a pass.
Set RB (bit 7) in the BIST command register to a 0 in order to end the internal BIST test.
Issue a software reset via the SR bit in the software reset register.
During BIST, the TTSI2K32T will corrupt traffic and the contents of the connection store memory. The TTSI2K32T
should, therefore, be taken off-line prior to running BIST and reprogrammed afterwards.
3.
4.
5.
Bit
7—1
0
Symbol
—
SR
Name/Description
Reserved.
Read as 0.
Software Reset.
Writing a 1 to this bit resets the chip. This bit has a function
similar to the RESET pin. When set to 1, all registers and control logic will be ini-
tialized to their default values except the software reset register. A 0 must be
written to this bit in order to clear and release the software reset. The micropro-
cessor interface will not be affected by the software reset, and the write to this bit
will terminate normally.
Bit
7
Symbol
RB
Name/Description
Run BIST.
Writing a 1 to this bit begins the built-in self-test for all internal mem-
ory blocks (i.e., the data and connection stores). This bit must be cleared by writ-
ing a 0 when BIST is complete. That event is indicated via the BIST complete
(BC) bit in the interrupt status register, as well as the BIST done (BD) bit in the
BIST command register. Writing a 0 to this bit position will also clear the BD bit. A
software reset should be performed after the BIST testing sequence is complete.
BIST Done (Read Only).
This bit indicates when the BIST test is complete. This
bit is used for polling to determine the completion of the BIST test. The real-time
duration of the TSI BIST test is 2.8 seconds. This bit will remain set to a 1 reflect-
ing the fact that the BIST is complete until the RB bit is written to a 0.
6
BD
5
BPF
BIST Pass/Fail (Read Only).
This bit indicates the status of the BIST test
results. A 0 indicates that no errors were detected.
Reserved.
Read as 0.
4—0
—
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