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參數(shù)資料
| 型號(hào)： | TTSI2K32T |
| 廠商： | Lineage Power |
| 英文描述： | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時(shí)隙交換機(jī)) |
| 中文描述： | 2048通道，32道時(shí)隙交換器（2048通道，32路干線時(shí)隙交換機(jī)） |
| 文件頁數(shù)： | 12/66頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TTSI2K32T |
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TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
12
Lucent Technologies Inc.
Pin Information
(continued)
* I
u
indicates internal 100 k
pull-up resistor, and I
d
indicates 17.5 k
pull-down resistor.
Table 4. TTSI2K32T Pin Descriptions
Symbol
RESET
Type
*
I
Description
Reset (Active-Low).
A low on this pin resets the TTSI2K32T. It is asynchronous to
any other clock or input signal. All flip-flops will be cleared when RESET is low. All
counters, state machines, and configuration registers will be set to the default state
following a reset.
Test (Active-Low).
When low, TEST causes the output and bidirectional pins of the
TTSI2K32T device to be in a high-impedance state. This pin has an internal pull-up
resistor.
Microprocessor Mode.
When MM = 0, the TTSI2K32T uses an asynchronous type
handshake (equal to mode 1 of the Lucent dual T1/E1 terminator devices). When
MM = 1, the TTSI2K32T uses a synchronous type handshake which requires a host
processor clock (PCLK) input. Both modes use a demultiplexed address and data
bus.
Synchronous Mode
(MM = 1)
Host Processor Clock.
Valid from
0 MHz to 65 MHz.
Address Valid (Active-Low).
Valid for
one PCLK cycle. Indicates the start of a
processor access.
TEST
I
u
MM
I
—
Asynchronous Mode
(MM = 0)
Unused.
Must be either tied high or low.
PCLK
I
AS
I
Address Valid (Active-Low).
Indicates
a valid address for a processor access.
Must be held low for the duration of the
access.
Chip Select (Active-Low).
This pin is
asserted low to enable any transfers
through the microprocessor interface.
CS should be a decode of all address
and cycle type signals defining the mem-
ory map location of the TTSI2K32T. In
this mode, CS is used to control the
tristating of DT at the end of the cycle.
The input timing requirement of CS rela-
tive to AS is described in the Timing
Characteristics section on page 56.
Data Valid (Active-Low).
Indicates valid
data during processor writes. The
TTSI2K32T will start driving D[7—0]
when this signal is asserted during pro-
cessor reads.
Data Transfer Acknowledge (Active-
Low).
Indicates that data has been writ-
ten during processor writes. Indicates
that read data is valid during processor
reads. Once driven active, this signal is
held active until AS , DS, or CS is
removed.
An external pull-up is required on this
output.
CS
I
Chip Select (Active-Low).
This pin is
asserted low to enable any transfers
through the microprocessor interface.
CS should be a decode of all address
and cycle type signals defining the mem-
ory map location of the TTSI2K32T.
DS
I
Not Used.
Must be tied high.
DT
O
Data Transfer Acknowledge (Active-
Low).
Active for one PCLK cycle. Indi-
cates that data has been written during
processor writes. Indicates that read
data is valid during processor reads.
An external pull-up is required on this
output.
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