參數(shù)資料
型號(hào)： TTSI1K16T
廠商： Lineage Power
英文描述： 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時(shí)隙交換機(jī))
中文描述： 1024通道，16道時(shí)隙交換器（1024通道，16路干線時(shí)隙交換機(jī)）
文件頁數(shù)： 62/64頁
文件大小： 1110K
代理商： TTSI1K16T
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
62
Lucent Technologies Inc.
Ordering Information
DS99-177PDH Replaces DS98-290TIC to Incorporate the Following Updates
1. Page 18, Highway Data Rate Selection section, added paragraph on meeting the 8.192 Mbits/s bandwidth
requirement for a transmit highway pair at the bottom of the page.
2. Page 20, updated Figure 10, Virtual and Physical Frames on page 20.
3. Page 22, Reset Sequence section, added paragraph on BIST requirement.
4. Page 23—page 26, Low-Latency and Frame-Integrity Modes section updated.
5. Page 27, Test-Pattern Generation section updated.
6. Page 27 and page 28, Test-Pattern Checking section updated.
7. Page 36, Table 15, General Command Register (0x00), removed last sentence in description of bit 2 and bit 1.
8. Page 36, Table 15, General Command Register (0x00), updated bit 0 symbol from GXEN to GXE.
9. Page 37, Table 16, Software Reset Register (0x01), updated bit 0, software reset description.
10. Page 39, Table 22, Interrupt Status Register (0x07), updated bit 4 and bit 2 to reserved status.
11. Page 40, Table 23, Interrupt Mask Register (0x08), updated bit 4 and bit 2 to reserved status.
12. Page 40, Table 23, Interrupt Mask Register (0x08), bit 3 symbol changed from MASKED to MASKERD.
13. Page 42, Table 25, Test-Pattern Style Register (0x0A), updated test-pattern descriptions.
14. Page 43, Table 26, Test-Pattern Checker Highway Register (0x0B), updated bit 4 to reserved status.
15. Page 43, Table 27, Test-Pattern Checker Upper Time-Slot Register (0x0C), updated description.
16. Page 43, Table 28, Test-Pattern Checker Lower Time-Slot Register (0x0D), updated description.
17. Page 43, Table 30, Test-Pattern Error Injection Register (0x0F), changed register name from test-pattern error
selection register to test-pattern error injection register and added sentence to end of description.
18. Page 45, Table 35, Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i), updated bit 3—bit 2 sym-
bol from XCEOFF to XFBOFF.
19. Page 46, Table 37, Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i), updated bit 2 symbol name
from XEN to XE.
20. Page 47, Table 38, Receive Highway Configuration Register (Byte 0) (0x1800 + 4i), updated bit 3—bit 2 symbol
from RCEOFF to RFBOFF.
21. Page 49, Transmit Highway 3-State Options section and Table 41, Transmit Highway 3-State Options updated.
22. Page 50, Data Store Memory section updated.
23. Page 51, Table 44, Connection Store Memory (Byte 0), changed TSA symbol to RTSA and updated
description.
24. Page 51, Table 45, Connection Store Memory (Byte 1), changed PORTNUM[4—0] symbol to RXHWY[3—0].
25. Page 51, Table 45, Connection Store Memory (Byte 1), updated bit 4 to reserved status.
26. Page 50—page 52, Connection Store Memory section updated.
27. Page 54, Table 46, Clock Specifications, updated clock period stability for CK.
28. Page 59, Timing Characteristics section, updated Figure 22, TDM Highway Timing and text.
29. Page 59, Table 50, TDM Highway Timing, timing parameter t26, minimum changed from 15 ns to 10 ns.
Device Code
Package
Temperature
Comcode
(Ordering Number)
108269762
TTSI1K16T3TL
144-pin TQFP
–40
°
C to +85
°
C
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