參數(shù)資料
型號： TTSI1K16T
廠商： Lineage Power
英文描述： 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機)
中文描述： 1024通道，16道時隙交換器（1024通道，16路干線時隙交換機）
文件頁數(shù)： 43/64頁
文件大?。?/td> 1110K
代理商： TTSI1K16T
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
43
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 26. Test-Pattern Checker Highway Register (0x0B)
Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C)
Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D)
Table 29. Test-Pattern Checker Data Register (0x0E)
Table 30. Test-Pattern Error Injection Register (0x0F)
Bit
7—4
3—0
Symbol
—
CHS[3—0]
Name/Description
Reserved.
Must be written to 0.
Checker Highway Select[3
—
0].
These 4 bits determine the receive highway to
which the test-pattern checker is connected.
Bit
7
6—0
Symbol
—
CKRUP[6—0]
Checker Upper Time-Slot Select[6
—
0].
These 7 bits determine the upper time
slot in the input highway to which the test-pattern checker is connected. All con-
tiguous time slots that lie between the lower and upper time-slot boundaries
inclusive are monitored for the test pattern. The range of time slots that can be
monitored is from 1 time slot to the entire span (32, 64, and 128 time slots for a
2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s highway, respectively). If one time
slot is to be monitored, then CKRUP and CKRLOW should be set to the same
value.
Name/Description
Reserved.
Bit
7
6—0
Symbol
—
CKRLOW
[6—0]
Name/Description
Reserved.
Checker Lower Time-Slot Select[6
—
0].
These 7 bits determine the lower time
slot in the input highway to which the test-pattern checker is connected. All con-
tiguous time slots that lie between the lower and upper time-slot boundaries
inclusive are monitored for the test pattern. The range of time slots that can be
monitored is from 1 time slot to the entire span (32, 64, and 128 time slots for a
2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s highway, respectively). If one time
slot is to be monitored, then CKRUP and CKRLOW should be set to the same
value.
Bit
7—0
Symbol
CTP[7—0]
Name/Description
Checker Test Pattern[7
—
0].
The data written here will be used for comparison
when the fixed mode is programmed into the test-pattern style register.
Bit
7—0
Symbol
BEC[7—0]
Name/Description
Bit Error Count[7
—
0].
This register is used to indicate the number of single bit
errors that are to be injected into the outgoing test pattern (QRSS, PRBS, or
fixed user-defined byte). This register can be programmed to inject up to 255 bit
errors. The BEI bit in the interrupt status register will indicate when all of the
errors have been injected. BEC[7—0] will automatically be reset when BEI is
set. In order to send out additional errors, BEC[7—0] should be rewritten. Errors
are injected at the rate of one per time slot.
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