參數(shù)資料
型號(hào)： TTSI1K16T
廠商： Lineage Power
英文描述： 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時(shí)隙交換機(jī))
中文描述： 1024通道，16道時(shí)隙交換器（1024通道，16路干線時(shí)隙交換機(jī)）
文件頁數(shù)： 25/64頁
文件大?。?/td> 1110K
代理商： TTSI1K16T
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
25
Lucent Technologies Inc.
Low-Latency and Frame-Integrity Modes
(continued)
Frame Integrity
(continued)
The range of Rx and Tx offsets can be independently selected from 0
μ
s to (125 –
)μ
s via the Rx and Tx highway
configuration registers, bytes 0 and 1, where
= 1/4 bit. The offset difference (Tx highway offset – Rx highway off-
set) can therefore take the range from
(125 –
)μ
s to +(125 –
)μ
s. The table below shows the virtual frame for
transmission for the various cases of offset difference.
Table 9. Offset Difference and Its Effect on Frame for Transmission
* The values for A, B, C, and D are specified in Table 10 below.
Table 10. Offset Difference Boundaries
Table 9 and Table 10 can be used to determine the latency of time slots through the TSI in a frame integrity situa-
tion. Keep in mind that the offset difference is the major factor in determining which virtual Tx frame the time slots
will go out in. The boundary values given in Table 10 are accurate to within ±1 time slot @ 8.192 Mbits/s (= ±4 bits
@ 4.096 Mbits/s = ±2 bits @ 2.048 Mbits/s) and will depend on your particular register settings.
This example can be used to determine the latency of a frame integrity situation. Keep in mind that only the Tx and
Rx highway offsets are relevant when determining the number of physical frames that the transmit data will incur.
However, there is a small range of offset separation where the data will go out in either virtual Tx frame N + 2 or
N + 3, depending on the actual Rx and Tx offsets chosen.
There may be many Rx/Tx highway pairs performing frame integrity simultaneously, but the definition of frame
integrity states that integrity is maintained between each Rx and Tx pair and not across multiple receive highways.
However, in practice, if a Tx highway contains FI time slots from multiple Rx highways and those Rx highways
have the same highway offset, then all of the FI time slots will incur equal delay with frame integrity through the
switch.
Offset Difference = (Tx Highway Offset – Rx Highway Offset)
Virtual Frame for Transmission
A
≤
offset difference < B*
B
≤
offset difference < C*
C
≤
offset difference
≤
D*
N + 3
N + 2
N + 1
Offset
Difference
Boundary
Boundary
Value
(
μ
s)
Boundary Value in Terms of Time Slots (ts) and Bits, at Different Data Rates
2.048 Mbits/s
4.096 Mbits/s
8.192 Mbits/s
A
B
C
D
(125
)
121.09375
+
3.90625
+
(125
)
(31 ts, 7 3/4 bits)
31 ts
1 ts
31 ts, 7 3/4 bits
(63 ts, 7 3/4 bits)
62 ts
2 ts
63 ts, 7 3/4 bits
(127 ts, 7 3/4 bits)
124 ts
4 ts
127 ts, 7 3/4 bits
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TTSI1K16T3TL 制造商:AGERE 制造商全稱:AGERE 功能描述:1024-Channel, 16-Highway Time-Slot Interchanger
TTSI1K16T3TL-DB 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述:
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TTSI2K32T3BAL 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger
TTSI4K32T 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger
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