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參數(shù)資料
| 型號： | TTSI1K16T |
| 廠商： | Lineage Power |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機) |
| 中文描述： | 1024通道，16道時隙交換器（1024通道，16路干線時隙交換機） |
| 文件頁數(shù)： | 27/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T |
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Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
27
Lucent Technologies Inc.
Test-Pattern Generation
Test-pattern generation involves selecting outgoing time slots on a particular transmit highway for use in transmit-
ting one of 15 patterns of data. The patterns available are selected using TPS[3—0] (bits 7—4) of the Test-Pattern
Style Register (0x0A), Table 25 on page 42. The transmit highway and time slots involved are selected using the
connection store.
Using the connection store, time slots can be set for test-pattern mode and the on-chip test-pattern generator will
be the source for that transmitted data. The type of test pattern used is determined by the values in the Test-Pat-
tern Style Register (0x0A), Table 25 on page 42. Test-pattern data can be applied to any number of time slots on
only one highway at a time. Any highway may be selected to transmit test-pattern data. The only restrictions for
selecting the time slots set for test-pattern mode are that the time slots must be from the same highway and they
must be contiguous.
The sequence for enabling test-pattern generation is as follows:
1.
Set TSDSM[2—0] (bits 7—5) in byte 1 of the connection store locations which correspond to the time slots
involved in test-pattern substitution mode. Any range of time slots may be selected for test-pattern substitution
mode, starting at any time-slot position. The remaining time slots of that highway will be unaffected.
Set TPS[3—0] (bits 7—4) of the Test-Pattern Style Register (0x0A), Table 25 on page 42 to select the test pat-
tern to be sent. If a fixed user-defined byte is selected for transmission via the TPS[3—0] bits, then the Test-
Pattern Generator Data Register (0x12), Table 33 on page 44 must also be programmed.
Select the data rate of the test-pattern generator via GENHDR[1—0] (bits 5—4) and set STTPG (bit 7) to 1 in
the Test Command Register (0x09), Table 24 on page 41 to start transmitting a good test pattern on the
selected time slots.
2.
3.
In order for data to be transmitted, highways need to be enabled using XE (bit 2) of the Transmit Highway Configu-
ration Register (Byte 2) (0x1002 + 4i), Table 37 on page 46 and GXE (bit 0) of the General Command Register
(0x00), Table 15 on page 36. This can be done before or after the above sequence.
The Tx highway that has been selected for test-pattern generation must be the only highway that has time slots
selected for test-pattern substitution mode (i.e., TSDSM[2—0] = 110) in the connection store. No time slots on any
other Tx highway may be selected for test-pattern substitution mode. If the Tx highway selected for test-pattern
generation is changed, then the previous highway must have all its time slots that were in the TSDSM[2—0] = 110
mode, to be changed to a non-test-pattern substitution mode.
Test-Pattern Checking
Test-pattern checking involves selecting incoming time slots on a particular receive highway for reception of one of
15 test patterns. The patterns available are selected by setting CPS[3—0] (bits 3—0) of the Test-Pattern Style
Register (0x0A), Table 25 on page 42. The input highway and time slots involved are selected using the following
registers:
I
Test-Pattern Checker Highway Register (0x0B), Table 26 on page 43
I
Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 27 on page 43
I
Test-Pattern Checker Lower Time-Slot Register (0x0D), Table 28 on page 43
Test-pattern data can be checked on any number of time slots on only one highway at a time. Any receive highway
may be selected to check for test-pattern data. The only restriction on selecting the time slots set for test-
pattern checking is that the time slots must be from the same highway and they must be contiguous.
The sequence for enabling test-pattern checking is as follows:
1.
Set Test-Pattern Checker Highway Register (0x0B), Table 26 on page 43 to select a highway for receiving the
test data.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TTSI1K16T3TL | 制造商:AGERE 制造商全稱:AGERE 功能描述:1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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