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| 型號： | TTSI1K16T |
| 廠商： | Lineage Power |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機(jī)) |
| 中文描述： | 1024通道，16道時隙交換器（1024通道，16路干線時隙交換機(jī)） |
| 文件頁數(shù)： | 24/64頁 |
| 文件大小： | 1110K |
| 代理商： | TTSI1K16T |
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TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
24
Lucent Technologies Inc.
Low-Latency and Frame-Integrity Modes
(continued)
Low Latency
(continued)
For example, consider any Rx highway running at 4.096 Mbits/s using time slot 5 to receive data, with an Rx high-
way offset of 3 time slots. It is to be transmitted on TXD6. The right hand side of the relationship evaluates to:
5
3
2
time slots @ 4.096 Mbits/s
time slots @ 4.096 Mbits/s
time slots @ 4.096 Mbits/s
+ (4 + 6) x 30.5176 ns
19,836.426 ns
+
+
The results of the calculation show that the received data can be transmitted with minimum delay using a Tx time
slot located 19,836.426 ns (or later) into the physical frame on TXD6. With a zero offset on TXD6, the time-slot
number for transmission with minimum delay would be:
Tx time slot 21 @ 8.192 Mbits/s
Tx time slot 11 @ 4.096 Mbits/s
Tx time slot 6 @ 2.048 Mbits/s
Frame Integrity
Frame integrity is applied to multiple transmit time slots in order to force data received in the same frame to be
transmitted together in a subsequent frame. This rule causes added delay, but it is useful for wideband data. Such
data could be ISDN BRI (2B channels) that take up two time slots on a receive highway. It could also be an ISDN
H0 channel (six contiguous time slots) that is being used to carry video.
The maximum latency through the device for any time slot marked for frame integrity mode is 378
μ
s. If that latency
is sufficient for a particular application, disregard any of the following details.
To understand the latency involved with frame-integrity mode, consider the following information. The definition of
frame integrity states that integrity is maintained between a particular Rx and Tx highway pair. This pair can be
made up of any Rx highway and any Tx highway.
Latency due to frame integrity mode is a function of the highway offsets of the Rx and Tx pair rather than the rela-
tive position of the time slots. Latency in this mode will be expressed in terms of physical frames. Whether time
slots received in virtual Rx frame N will end up going out in virtual Tx frame N + 1, N + 2, or N + 3 is dependent on
the relative highway Rx and Tx highway offsets. For a description of virtual frames, see Figure 10, Virtual and
Physical Frames on page 20.
Consider the following example. Assume RXD0 is switched to TXD1 with all Tx time slots marked for frame integ-
rity (FI) on TXD1. If it is desirable to have the lowest possible latency for the data received on RXD0, then TXD1
must have a highway offset which is 3.90625
μ
s (1 time slot @ 2.048 Mbits/s) greater than the highway offset
selected for RXD0. In that case, time slots received in the virtual Rx frame (frame N) will be transmitted in the next
virtual Tx frame (frame N + 1).
The greatest latency will be incurred when the RXD0 offset is at least 121.09375
μ
s (31 time slots @
2.048 Mbits/s) greater than the offset selected for TXD1. In that case, time slots received in the current virtual Rx
frame (frame N) will be transmitted three frames later, i.e., in virtual Tx frame N + 3.
For all other RXD0 and TXD1 offset values, time slots received in the current virtual Rx frame will be transmitted
two frames later, i.e., in virtual Tx frame N + 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機(jī)) |
| TTSI4K32T | 4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 4096-Channel, 32-Highway Time-Slot Interchanger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL | 制造商:AGERE 制造商全稱:AGERE 功能描述:1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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