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參數(shù)資料
| 型號： | TTSI1K16T |
| 廠商： | Lineage Power |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機) |
| 中文描述： | 1024通道，16道時隙交換器（1024通道，16路干線時隙交換機） |
| 文件頁數(shù)： | 46/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T |
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TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
46
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i)
*
* i = the transmit highway number.
Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i)
*
* i = the transmit highway number.
Note
: During CK input interruptions (e.g., clock switching), the transmit highways should be 3-stated by clearing
the GXE (bit 0) of the general command register. The highways can be enabled by writing a 1 to the GXE bit
once the PLL has regained lock (250
μ
s later).
Bit
7
6—0
Symbol
—
XTSOFF
[6—0]
Name/Description
Reserved.
Read as 0.
Transmit Highway Time-Slot Offset[6
—
0].
XTSOFF is used to offset the
beginning of an outgoing frame by the indicated number of time slots (bytes). If
no time-slot offsetting is required, these bits should be set to zero. The following
table shows the range of offsets for the different highway data rates.
Highway Data Rate Time-Slot Offset Range
2.048 Mbits/s 0—31
4.096 Mbits/s 0—63
8.192 Mbits/s 0—127
Note:
A time slot is always 8 bits. A bit period is relative to the highway data rate
set for each highway.
XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of
the outgoing frame. The values are added together to position the transmission
of time slot 0, bit 0.
Bit
7—3
2
Symbol
—
XE
Name/Description
Reserved.
Read as 0.
Transmit Highway 3-State Enable
. The associated output highway is high
impedance when this bit is 0 (default after reset). When this bit is set to 1, the
output driver is enabled. The effect of this bit is dependent on the status of the
external drive bit of the general command register. See Table 15, General
Command Register (0x00), on page 36 for details. For other methods of 3-stat-
ing transmit highways, see Table 41, Transmit Highway 3-State Options, on
page 49.
Transmit Highway Data Rate[1—0].
HDR1
HDR0
0
0
2.048 Mbits/s (default)
0
1
4.096 Mbits/s
1
0
8.192 Mbits/s
1
1
0.000 Mbits/s (idle, not transmitting data)
1—0
HDR[1—0]
All of the transmit highways are grouped into pairs. TXD0 with TXD1, TXD2
with TXD3, . . . , and TXD14 with TXD15. The maximum combined bandwidth
for each pair is 8.192 Mbits/s. Refer to Table 7, Tx Highway Data Rate Options,
on page 18 for highway rate combination.
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PDF描述 |
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| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
| TTSI4K32T | 4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 4096-Channel, 32-Highway Time-Slot Interchanger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL | 制造商:AGERE 制造商全稱:AGERE 功能描述:1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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