參數(shù)資料
型號: TTSI1K16T
廠商: Lineage Power
英文描述: 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機(jī))
中文描述: 1024通道,16道時隙交換器(1024通道,16路干線時隙交換機(jī))
文件頁數(shù): 33/64頁
文件大?。?/td> 1110K
代理商: TTSI1K16T
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
33
Lucent Technologies Inc.
JTAG Boundary-Scan Specification
(continued)
Instruction Register
(continued)
BYPASS:
This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS reg-
ister is selected after the UPDATE IR. The BS register is in normal mode. A 0 is clocked into the BYPASS register
during CAPTURE DR state. Data can be shifted by the BYPASS register during SHIFT DR. The contents of the BS
register do not change in the UPDATE DR state. Please note that a 0 that was loaded during CAPTURE DR
appears first when the data is being read out.
Boundary-Scan Register
The boundary-scan register is a shift register, whereby one or more BS cells are assigned to every digital
TTSI1K16T pin. The TTSI1K16T’s boundary-scan register bit-to-pin assignment is defined in the BSDL file, which
is available upon request.
BYPASS Register
The BYPASS register is a one-stage shift register that enables the shift chain to be reduced to one stage in the
TTSI1K16T.
IDCODE Register
The IDCODE register identifies the TTSI1K16T by means of a parallel, loadable, 32-bit shift register. The code is
loaded on the rising edge of TCK in the CAPTURE DR state. The contents of this register is indicated in the BSDL
file.
3-State Procedures
The 3-state input participates in the boundary scan. It has a BS cell, but buffer blocking via this input is suppressed
for the EXTEST instruction. The 3-state input is regarded as a signal input that is to participate in the connection
test during EXTEST. The buffer blocking function should not be active during EXTEST to ensure that the update
pattern at the TTSI1K16T outputs does not become corrupted.
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